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-rw-r--r--tests/simple/attrib08_mod_inst.v22
1 files changed, 22 insertions, 0 deletions
diff --git a/tests/simple/attrib08_mod_inst.v b/tests/simple/attrib08_mod_inst.v
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+++ b/tests/simple/attrib08_mod_inst.v
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+module bar(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output reg out;
+
+ always @(posedge clk)
+ if (rst) out <= 1'd0;
+ else out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output wire out;
+
+ (* my_module_instance = 99 *)
+ bar bar_instance (clk, rst, inp, out);
+endmodule
+