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-rw-r--r--tests/sim/adff.v7
1 files changed, 7 insertions, 0 deletions
diff --git a/tests/sim/adff.v b/tests/sim/adff.v
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+module adff( input d, clk, rst, output reg q );
+ always @( posedge clk, posedge rst )
+ if (rst)
+ q <= 0;
+ else
+ q <= d;
+endmodule