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-rw-r--r--tests/opt/ice40_carry.v3
-rw-r--r--tests/opt/opt_lut.ys2
2 files changed, 1 insertions, 4 deletions
diff --git a/tests/opt/ice40_carry.v b/tests/opt/ice40_carry.v
deleted file mode 100644
index ed938932a..000000000
--- a/tests/opt/ice40_carry.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module SB_CARRY (output CO, input I0, I1, CI);
- assign CO = (I0 && I1) || ((I0 || I1) && CI);
-endmodule
diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys
index f3c1e2822..59b12c351 100644
--- a/tests/opt/opt_lut.ys
+++ b/tests/opt/opt_lut.ys
@@ -1,4 +1,4 @@
read_verilog opt_lut.v
synth_ice40
ice40_unlut
-equiv_opt -map ice40_carry.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
+equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3