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-rw-r--r--tests/ice40/dffs.ys6
1 files changed, 2 insertions, 4 deletions
diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys
index 0fa0bc3eb..ddd8e5734 100644
--- a/tests/ice40/dffs.ys
+++ b/tests/ice40/dffs.ys
@@ -1,11 +1,9 @@
read_verilog dffs.v
-proc
-flatten
-dff2dffe
hierarchy -top top
synth -flatten -run coarse # technology-independent coarse grained synthesis
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFF
-select -assert-none t:SB_DFF %% t:* %D
+select -assert-count 1 t:SB_DFFE
+select -assert-none t:SB_DFF t:SB_DFFE %% t:* %D