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Diffstat (limited to 'tests/ice40/add_sub.ys')
| -rw-r--r-- | tests/ice40/add_sub.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/ice40/add_sub.ys b/tests/ice40/add_sub.ys index 8eeb221db..4a998d98d 100644 --- a/tests/ice40/add_sub.ys +++ b/tests/ice40/add_sub.ys @@ -1,6 +1,6 @@ read_verilog add_sub.v hierarchy -top top -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 11 t:SB_LUT4 |