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-rw-r--r--tests/efinix/dffs.ys24
1 files changed, 0 insertions, 24 deletions
diff --git a/tests/efinix/dffs.ys b/tests/efinix/dffs.ys
deleted file mode 100644
index cdd288233..000000000
--- a/tests/efinix/dffs.ys
+++ /dev/null
@@ -1,24 +0,0 @@
-read_verilog dffs.v
-design -save read
-
-hierarchy -top dff
-proc
-equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd dff # Constrain all select calls below inside the top module
-select -assert-count 1 t:EFX_FF
-select -assert-count 1 t:EFX_GBUFCE
-
-select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
-
-design -load read
-hierarchy -top dffe
-proc
-equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd dffe # Constrain all select calls below inside the top module
-select -assert-count 1 t:EFX_FF
-select -assert-count 1 t:EFX_GBUFCE
-select -assert-count 1 t:EFX_LUT4
-
-select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D