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-rw-r--r--tests/ecp5/fsm.ys4
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/ecp5/fsm.ys b/tests/ecp5/fsm.ys
index 6368edc57..ded91e5f7 100644
--- a/tests/ecp5/fsm.ys
+++ b/tests/ecp5/fsm.ys
@@ -1,10 +1,10 @@
read_verilog fsm.v
-hierarchy -top top
+hierarchy -top fsm
proc
flatten
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd fsm # Constrain all select calls below inside the top module
select -assert-count 1 t:L6MUX21
select -assert-count 13 t:LUT4
select -assert-count 5 t:PFUMX