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diff --git a/tests/ecp5/counter.ys b/tests/ecp5/counter.ys
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-read_verilog counter.v
-hierarchy -top top
-proc
-flatten
-equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 4 t:CCU2C
-select -assert-count 8 t:TRELLIS_FF
-select -assert-none t:CCU2C t:TRELLIS_FF %% t:* %D