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-rw-r--r--tests/ecp5/adffs.ys41
1 files changed, 36 insertions, 5 deletions
diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys
index fc1363a32..658f302d0 100644
--- a/tests/ecp5/adffs.ys
+++ b/tests/ecp5/adffs.ys
@@ -1,9 +1,40 @@
read_verilog adffs.v
+design -save read
+
proc
-flatten
-equiv_opt -multiclock -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+hierarchy -top adff
+equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 4 t:TRELLIS_FF
-select -assert-count 3 t:LUT4
+cd adff # Constrain all select calls below inside the top module
+select -assert-count 1 t:TRELLIS_FF
+select -assert-none t:TRELLIS_FF %% t:* %D
+
+design -load read
+proc
+hierarchy -top adffn
+equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adffn # Constrain all select calls below inside the top module
+select -assert-count 1 t:TRELLIS_FF
+select -assert-count 1 t:LUT4
+select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
+
+design -load read
+proc
+hierarchy -top dffs
+equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffs # Constrain all select calls below inside the top module
+select -assert-count 1 t:TRELLIS_FF
+select -assert-count 1 t:LUT4
+select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
+
+design -load read
+proc
+hierarchy -top ndffnr
+equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd ndffnr # Constrain all select calls below inside the top module
+select -assert-count 1 t:TRELLIS_FF
+select -assert-count 1 t:LUT4
select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D