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Diffstat (limited to 'tests/arch/nexus/add_sub.ys')
-rw-r--r-- | tests/arch/nexus/add_sub.ys | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/tests/arch/nexus/add_sub.ys b/tests/arch/nexus/add_sub.ys new file mode 100644 index 000000000..4317bab81 --- /dev/null +++ b/tests/arch/nexus/add_sub.ys @@ -0,0 +1,21 @@ +read_verilog ../common/add_sub.v +hierarchy -top top +proc +design -save orig + +equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +stat +select -assert-count 10 t:LUT4 +select -assert-none t:IB t:OB t:VLO t:LUT4 %% t:* %D + +design -load orig + +equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus -abc9 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +stat +select -assert-count 6 t:LUT4 +select -assert-count 4 t:WIDEFN9 +select -assert-none t:IB t:OB t:VLO t:LUT4 t:WIDEFN9 %% t:* %D |