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-rw-r--r--tests/arch/machxo2/mux.ys8
1 files changed, 4 insertions, 4 deletions
diff --git a/tests/arch/machxo2/mux.ys b/tests/arch/machxo2/mux.ys
index 7b7e62d4c..27bffbe63 100644
--- a/tests/arch/machxo2/mux.ys
+++ b/tests/arch/machxo2/mux.ys
@@ -7,7 +7,7 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux2 # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT4
-select -assert-none t:LUT4 t:FACADE_IO %% t:* %D
+select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
design -load read
hierarchy -top mux4
@@ -17,7 +17,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 2 t:LUT4
-select -assert-none t:LUT4 t:FACADE_IO %% t:* %D
+select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
design -load read
hierarchy -top mux8
@@ -27,7 +27,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 5 t:LUT4
-select -assert-none t:LUT4 t:FACADE_IO %% t:* %D
+select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
design -load read
hierarchy -top mux16
@@ -37,4 +37,4 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd mux16 # Constrain all select calls below inside the top module
select -assert-max 12 t:LUT4
-select -assert-none t:LUT4 t:FACADE_IO %% t:* %D
+select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D