diff options
Diffstat (limited to 'tests/arch/ice40/memories.ys')
| -rw-r--r-- | tests/arch/ice40/memories.ys | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/tests/arch/ice40/memories.ys b/tests/arch/ice40/memories.ys index c32f12315..a0b0f95b2 100644 --- a/tests/arch/ice40/memories.ys +++ b/tests/arch/ice40/memories.ys @@ -65,25 +65,25 @@ design -reset; read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp setattr -set syn_romstyle "ebr" m:memory synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp -select -assert-count 1 t:$mem # requested BROM but this is a RAM +select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM design -reset; read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp setattr -set rom_block 1 m:memory synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp -select -assert-count 1 t:$mem # requested BROM but this is a RAM +select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM design -reset; read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp setattr -set syn_ramstyle "block_ram" m:memory synth_ice40 -top sync_ram_sdp -nobram; cd sync_ram_sdp -select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled +select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled design -reset; read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp setattr -set ram_block 1 m:memory synth_ice40 -top sync_ram_sdp -nobram; cd sync_ram_sdp -select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled +select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled # ================================ ROM ================================ # ROM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K @@ -146,22 +146,22 @@ design -reset; read_verilog ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom setattr -set syn_ramstyle "block_ram" m:memory synth_ice40 -top sync_rom; cd sync_rom -select -assert-count 1 t:$mem # requested BRAM but this is a ROM +select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM design -reset; read_verilog ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom setattr -set ram_block 1 m:memory synth_ice40 -top sync_rom; cd sync_rom -select -assert-count 1 t:$mem # requested BRAM but this is a ROM +select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM design -reset; read_verilog ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom setattr -set syn_romstyle "ebr" m:memory synth_ice40 -top sync_rom -nobram; cd sync_rom -select -assert-count 1 t:$mem # requested BROM but BRAM is disabled +select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled design -reset; read_verilog ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom setattr -set rom_block 1 m:memory synth_ice40 -top sync_rom -nobram; cd sync_rom -select -assert-count 1 t:$mem # requested BROM but BRAM is disabled +select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled |