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Diffstat (limited to 'tests/arch/ice40/latches.ys')
| -rw-r--r-- | tests/arch/ice40/latches.ys | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/tests/arch/ice40/latches.ys b/tests/arch/ice40/latches.ys new file mode 100644 index 000000000..708734e44 --- /dev/null +++ b/tests/arch/ice40/latches.ys @@ -0,0 +1,12 @@ +read_verilog latches.v + +proc +flatten +# Can't run any sort of equivalence check because latches are blown to LUTs +#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check + +#design -load preopt +synth_ice40 +cd top +select -assert-count 4 t:SB_LUT4 +select -assert-none t:SB_LUT4 %% t:* %D |