1 files changed, 0 insertions, 30 deletions
diff --git a/techlibs/xilinx/xc6s_cells_xtra.v b/techlibs/xilinx/xc6s_cells_xtra.v
index 014e73df0..f8dcce81d 100644
--- a/techlibs/xilinx/xc6s_cells_xtra.v
+++ b/techlibs/xilinx/xc6s_cells_xtra.v
@@ -1793,36 +1793,6 @@ module IDDR2 (...);
     input S;
 endmodule
 
-module LDCE (...);
-    parameter [0:0] INIT = 1'b0;
-    parameter [0:0] IS_CLR_INVERTED = 1'b0;
-    parameter [0:0] IS_G_INVERTED = 1'b0;
-    parameter MSGON = "TRUE";
-    parameter XON = "TRUE";
-    output Q;
-    (* invertible_pin = "IS_CLR_INVERTED" *)
-    input CLR;
-    input D;
-    (* invertible_pin = "IS_G_INVERTED" *)
-    input G;
-    input GE;
-endmodule
-
-module LDPE (...);
-    parameter [0:0] INIT = 1'b1;
-    parameter [0:0] IS_G_INVERTED = 1'b0;
-    parameter [0:0] IS_PRE_INVERTED = 1'b0;
-    parameter MSGON = "TRUE";
-    parameter XON = "TRUE";
-    output Q;
-    input D;
-    (* invertible_pin = "IS_G_INVERTED" *)
-    input G;
-    input GE;
-    (* invertible_pin = "IS_PRE_INVERTED" *)
-    input PRE;
-endmodule
-
 module ODDR2 (...);
     parameter DDR_ALIGNMENT = "NONE";
     parameter [0:0] INIT = 1'b0;