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-rw-r--r--techlibs/xilinx/synth_xilinx.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 4011e09b0..bb3ced8da 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -619,8 +619,8 @@ struct SynthXilinxPass : public ScriptPass
if (dff_mode)
techmap_args += " -D DFF_MODE";
run("techmap " + techmap_args);
- run("read_verilog -icells -specify -lib +/xilinx/abc9_model.v");
- std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
+ run("read_verilog -icells -lib -specify +/xilinx/abc9_model.v");
+ std::string abc9_opts;
auto k = stringf("synth_xilinx.abc9.%s.W", family.c_str());
if (active_design->scratchpad.count(k))
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());