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-rw-r--r--techlibs/quicklogic/synth_quicklogic.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc
index 754de2de6..94bd44db0 100644
--- a/techlibs/quicklogic/synth_quicklogic.cc
+++ b/techlibs/quicklogic/synth_quicklogic.cc
@@ -48,8 +48,8 @@ struct SynthQuickLogicPass : public ScriptPass {
log(" is omitted if this parameter is not specified.\n");
log("\n");
log(" -verilog <file>\n");
- log(" write the design to the specified verilog file. writing of an output file\n");
- log(" is omitted if this parameter is not specified.\n");
+ log(" write the design to the specified verilog file. writing of an output\n");
+ log(" file is omitted if this parameter is not specified.\n");
log("\n");
log(" -abc\n");
log(" use old ABC flow, which has generally worse mapping results but is less\n");