1 files changed, 8 insertions, 5 deletions
diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc
index 43d3592d5..c33eb43bf 100644
--- a/techlibs/intel_alm/synth_intel_alm.cc
+++ b/techlibs/intel_alm/synth_intel_alm.cc
@@ -43,21 +43,24 @@ struct SynthIntelALMPass : public ScriptPass {
 		log("    -family <family>\n");
 		log("        target one of:\n");
 		log("        \"cyclonev\"    - Cyclone V (default)\n");
-		log("        \"arriav\"      - Arria V (non-GZ)");
+		log("        \"arriav\"      - Arria V (non-GZ)\n");
 		log("        \"cyclone10gx\" - Cyclone 10GX\n");
 		log("\n");
 		log("    -vqm <file>\n");
-		log("        write the design to the specified Verilog Quartus Mapping File. Writing of an\n");
-		log("        output file is omitted if this parameter is not specified. Implies -quartus.\n");
+		log("        write the design to the specified Verilog Quartus Mapping File. Writing\n");
+		log("        of an output file is omitted if this parameter is not specified. Implies\n");
+		log("        -quartus.\n");
 		log("\n");
 		log("    -noflatten\n");
-		log("        do not flatten design before synthesis; useful for per-module area statistics\n");
+		log("        do not flatten design before synthesis; useful for per-module area\n");
+		log("        statistics\n");
 		log("\n");
 		log("    -quartus\n");
 		log("        output a netlist using Quartus cells instead of MISTRAL_* cells\n");
 		log("\n");
 		log("    -dff\n");
-		log("        pass DFFs to ABC to perform sequential logic optimisations (EXPERIMENTAL)\n");
+		log("        pass DFFs to ABC to perform sequential logic optimisations\n");
+		log("        (EXPERIMENTAL)\n");
 		log("\n");
 		log("    -run <from_label>:<to_label>\n");
 		log("        only run the commands between the labels (see below). an empty\n");