diff options
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/ice40_braminit.cc | 4 | ||||
| -rw-r--r-- | techlibs/ice40/ice40_ffinit.cc | 4 | ||||
| -rw-r--r-- | techlibs/ice40/ice40_ffssr.cc | 4 | ||||
| -rw-r--r-- | techlibs/ice40/ice40_opt.cc | 4 | ||||
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 10 |
5 files changed, 13 insertions, 13 deletions
diff --git a/techlibs/ice40/ice40_braminit.cc b/techlibs/ice40/ice40_braminit.cc index 936c189ea..e5d1f7e24 100644 --- a/techlibs/ice40/ice40_braminit.cc +++ b/techlibs/ice40/ice40_braminit.cc @@ -128,7 +128,7 @@ static void run_ice40_braminit(Module *module) struct Ice40BRAMInitPass : public Pass { Ice40BRAMInitPass() : Pass("ice40_braminit", "iCE40: perform SB_RAM40_4K initialization from file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -138,7 +138,7 @@ struct Ice40BRAMInitPass : public Pass { log("parameter and converts it into the required INIT_x attributes\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { log_header(design, "Executing ICE40_BRAMINIT pass.\n"); diff --git a/techlibs/ice40/ice40_ffinit.cc b/techlibs/ice40/ice40_ffinit.cc index d7715135e..2eef3fa93 100644 --- a/techlibs/ice40/ice40_ffinit.cc +++ b/techlibs/ice40/ice40_ffinit.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct Ice40FfinitPass : public Pass { Ice40FfinitPass() : Pass("ice40_ffinit", "iCE40: handle FF init values") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -35,7 +35,7 @@ struct Ice40FfinitPass : public Pass { log("nonzero init values.\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { log_header(design, "Executing ICE40_FFINIT pass (implement FF init values).\n"); diff --git a/techlibs/ice40/ice40_ffssr.cc b/techlibs/ice40/ice40_ffssr.cc index ffb8c74b1..492029b77 100644 --- a/techlibs/ice40/ice40_ffssr.cc +++ b/techlibs/ice40/ice40_ffssr.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct Ice40FfssrPass : public Pass { Ice40FfssrPass() : Pass("ice40_ffssr", "iCE40: merge synchronous set/reset into FF cells") { } - void help() YS_OVERRIDE + void help() override { log("\n"); log(" ice40_ffssr [options] [selection]\n"); @@ -33,7 +33,7 @@ struct Ice40FfssrPass : public Pass { log("Merge synchronous set/reset $_MUX_ cells into iCE40 FFs.\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { log_header(design, "Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).\n"); diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 18c1a58cf..1a70fa8c0 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -203,7 +203,7 @@ static void run_ice40_opts(Module *module) struct Ice40OptPass : public Pass { Ice40OptPass() : Pass("ice40_opt", "iCE40: perform simple optimizations") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -220,7 +220,7 @@ struct Ice40OptPass : public Pass { log(" while <changed design>\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { string opt_expr_args = "-mux_undef -undriven"; diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 27850b075..f2fc1ca6d 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -29,14 +29,14 @@ struct SynthIce40Pass : public ScriptPass { SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { } - void on_register() YS_OVERRIDE + void on_register() override { RTLIL::constpad["synth_ice40.abc9.hx.W"] = "250"; RTLIL::constpad["synth_ice40.abc9.lp.W"] = "400"; RTLIL::constpad["synth_ice40.abc9.u.W"] = "750"; } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -119,7 +119,7 @@ struct SynthIce40Pass : public ScriptPass bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr, abc9, dff, flowmap; int min_ce_use; - void clear_flags() YS_OVERRIDE + void clear_flags() override { top_opt = "-auto-top"; blif_file = ""; @@ -140,7 +140,7 @@ struct SynthIce40Pass : public ScriptPass device_opt = "hx"; } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { string run_from, run_to; clear_flags(); @@ -262,7 +262,7 @@ struct SynthIce40Pass : public ScriptPass log_pop(); } - void script() YS_OVERRIDE + void script() override { std::string define; if (device_opt == "lp") |