6 files changed, 13 insertions, 13 deletions
diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index 994f3091d..a0655643d 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -4,7 +4,7 @@
 
 # Inputs: C D
 # Outputs: Q
-SB_DFF 1 1 2 1
+SB_DFF 1 0 2 1
 - -
 
 # Inputs: C D E
@@ -109,5 +109,5 @@ SB_CARRY 21 1 3 1
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 22 0 4 1
+SB_LUT4 22 1 4 1
 449 400 379 316
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index 002b7bba4..dbc98d0c4 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -4,7 +4,7 @@
 
 # Inputs: C D
 # Outputs: Q
-SB_DFF 1 1 2 1
+SB_DFF 1 0 2 1
 - -
 
 # Inputs: C D E
@@ -109,5 +109,5 @@ SB_CARRY 21 1 3 1
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 22 0 4 1
+SB_LUT4 22 1 4 1
 465 558 589 661
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index cb336181c..3b5834e40 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -4,7 +4,7 @@
 
 # Inputs: C D
 # Outputs: Q
-SB_DFF 1 1 2 1
+SB_DFF 1 0 2 1
 - -
 
 # Inputs: C D E
@@ -109,5 +109,5 @@ SB_CARRY 21 1 3 1
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 22 0 4 1
+SB_LUT4 22 1 4 1
 1285 1231 1205 874
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index 287c48b11..759549e30 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -53,7 +53,7 @@ module \$lut (A, Y);
     end else
     if (WIDTH == 4) begin
       localparam [15:0] INIT = {LUT[15], LUT[7], LUT[11], LUT[3], LUT[13], LUT[5], LUT[9], LUT[1], LUT[14], LUT[6], LUT[10], LUT[2], LUT[12], LUT[4], LUT[8], LUT[0]};
-      SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
+      SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
         .I0(A[3]), .I1(A[2]), .I2(A[1]), .I3(A[0]));
     end else begin
       wire _TECHMAP_FAIL_ = 1;
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 560008bc4..523dd8cbe 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -127,7 +127,7 @@ endmodule
 
 // SiliconBlue Logic Cells
 
-(* abc_box_id = 22 *)
+(* abc_box_id = 22, lib_whitebox *)
 module SB_LUT4 (output O, input I0, I1, I2, I3);
 	parameter [15:0] LUT_INIT = 0;
 	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@@ -136,8 +136,8 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 21, lib_whitebox *)
-module SB_CARRY (output CO, input I0, I1, CI);
+(* abc_box_id = 21, abc_carry, lib_whitebox *)
+module SB_CARRY ((* abc_carry_out *) output CO, input I0, I1, (* abc_carry_in *) input CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
@@ -145,7 +145,7 @@ endmodule
 
 (* abc_box_id = 1, abc_flop, lib_whitebox *)
 module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
-`ifndef ABC_MODEL
+`ifndef _ABC
 	always @(posedge C)
 		Q <= D;
 `else
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 168161a90..5afa042b0 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib -D ABC_MODEL +/ice40/cells_sim.v");
+			run("read_verilog -lib -D_ABC +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
@@ -334,7 +334,7 @@ struct SynthIce40Pass : public ScriptPass
 				if (abc == "abc9")
 					run(abc + stringf(" -dress -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
 				else
-					run(abc + " -lut 4", "(skip if -noabc)");
+					run(abc + " -dress -lut 4", "(skip if -noabc)");
 			}
 			run("clean");
 			if (relut || help_mode) {