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-rw-r--r--techlibs/ecp5/synth_ecp5.cc10
1 files changed, 5 insertions, 5 deletions
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index aceb36abc..c9451e76b 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -30,12 +30,12 @@ struct SynthEcp5Pass : public ScriptPass
{
SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
- void on_register() YS_OVERRIDE
+ void on_register() override
{
RTLIL::constpad["synth_ecp5.abc9.W"] = "300";
}
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -112,7 +112,7 @@ struct SynthEcp5Pass : public ScriptPass
string top_opt, blif_file, edif_file, json_file;
bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, nodsp, vpr;
- void clear_flags() YS_OVERRIDE
+ void clear_flags() override
{
top_opt = "-auto-top";
blif_file = "";
@@ -133,7 +133,7 @@ struct SynthEcp5Pass : public ScriptPass
nodsp = false;
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@@ -239,7 +239,7 @@ struct SynthEcp5Pass : public ScriptPass
log_pop();
}
- void script() YS_OVERRIDE
+ void script() override
{
if (check_label("begin"))
{