diff options
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/cmds/select.cc | 2 | ||||
| -rw-r--r-- | passes/fsm/fsm_detect.cc | 2 | ||||
| -rw-r--r-- | passes/hierarchy/submod.cc | 4 | ||||
| -rw-r--r-- | passes/proc/proc_dff.cc | 4 | ||||
| -rw-r--r-- | passes/sat/eval.cc | 2 | ||||
| -rw-r--r-- | passes/sat/sat.cc | 4 |
6 files changed, 9 insertions, 9 deletions
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 8e42fe15f..7f841673f 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -532,7 +532,7 @@ static void select_op_expand(RTLIL::Design *design, std::string arg, char mode) } if (rem_objects == 0) - log("Warning: reached configured limit at `%s'.\n", arg.c_str()); + log_warning("reached configured limit at `%s'.\n", arg.c_str()); } static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &sel) diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 84932e963..c89553c6b 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -43,7 +43,7 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig return true; if (recursion_monitor.check_any(sig)) { - log("Warning: logic loop in mux tree at signal %s in module %s.\n", + log_warning("logic loop in mux tree at signal %s in module %s.\n", log_signal(sig), RTLIL::id2cstr(module->name)); return false; } diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 68a441f40..8d4012c53 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -85,7 +85,7 @@ struct SubmodWorker for (auto &conn : cell->connections()) flag_signal(conn.second, true, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first), false, false); } else { - log("WARNING: Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str()); + log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str()); for (auto &conn : cell->connections()) flag_signal(conn.second, true, true, true, false, false); } @@ -102,7 +102,7 @@ struct SubmodWorker for (auto &conn : cell->connections()) flag_signal(conn.second, false, false, false, true, true); if (flag_found_something) - log("WARNING: Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str()); + log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str()); } } diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index b632cdabb..76842da6b 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -333,12 +333,12 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) if (many_async_rules.size() > 0) { - log("WARNING: Complex async reset for dff `%s'.\n", log_signal(sig)); + log_warning("Complex async reset for dff `%s'.\n", log_signal(sig)); gen_dffsr_complex(mod, insig, sig, sync_edge->signal, sync_edge->type == RTLIL::SyncType::STp, many_async_rules, proc); } else if (!rstval.is_fully_const() && !ce.eval(rstval)) { - log("WARNING: Async reset value `%s' is not constant!\n", log_signal(rstval)); + log_warning("Async reset value `%s' is not constant!\n", log_signal(rstval)); gen_dffsr(mod, insig, rstval, sig, sync_edge->type == RTLIL::SyncType::STp, sync_level && sync_level->type == RTLIL::SyncType::ST1, diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 7a5a02a9b..62534ec0b 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -277,7 +277,7 @@ struct VlogHammerReporter while (!ce.eval(sig, undef)) { // log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", RTLIL::id2cstr(module->name), log_signal(sig), log_signal(undef)); - log("Warning: Setting signal %s in module %s to undef.\n", log_signal(undef), RTLIL::id2cstr(module->name)); + log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), RTLIL::id2cstr(module->name)); ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size())); } diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index d5d1d9160..b73417e87 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -116,7 +116,7 @@ struct SatHelper } if (removed_bits.size()) - log("Warning: ignoring initial value on non-register: %s\n", log_signal(removed_bits)); + log_warning("ignoring initial value on non-register: %s\n", log_signal(removed_bits)); if (lhs.size()) { log("Import set-constraint from init attribute: %s = %s\n", log_signal(lhs), log_signal(rhs)); @@ -327,7 +327,7 @@ struct SatHelper show_drivers.insert(sigmap(p.second), c.second); import_cell_counter++; } else if (ignore_unknown_cells) - log("Warning: Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type)); + log_warning("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type)); else log_error("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type)); } |