diff options
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/memory/memory_collect.cc | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index ca1a3666f..ad4df228e 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -20,9 +20,19 @@ #include "kernel/register.h" #include "kernel/log.h" #include <sstream> +#include <algorithm> #include <stdlib.h> #include <assert.h> +static bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b) +{ + if (a->type == "$memrd" && b->type == "$memrd") + return a->name < b->name; + if (a->type == "$memrd" || b->type == "$memrd") + return (a->type == "$memrd") < (b->type == "$memrd"); + return a->parameters.at("\\PRIORITY").as_int() < b->parameters.at("\\PRIORITY").as_int(); +} + static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) { log("Collecting $memrd and $memwr for memory `%s' in module `%s':\n", @@ -48,11 +58,18 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) RTLIL::SigSpec sig_rd_data; std::vector<std::string> del_cell_ids; + std::vector<RTLIL::Cell*> memcells; - for (auto &cell_it : module->cells) - { + for (auto &cell_it : module->cells) { RTLIL::Cell *cell = cell_it.second; + if ((cell->type == "$memwr" || cell->type == "$memrd") && cell->parameters["\\MEMID"].decode_string() == memory->name) + memcells.push_back(cell); + } + + std::sort(memcells.begin(), memcells.end(), memcells_cmp); + for (auto cell : memcells) + { if (cell->type == "$memwr" && cell->parameters["\\MEMID"].decode_string() == memory->name) { wr_ports++; |