diff options
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9.cc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index f7f2e862a..69b0c1192 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -511,6 +511,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri // Remove all AND, NOT, and ABC box instances // in preparation for stitching mapped_mod in + // Short $_DFF_[NP]_ cells used by ABC (FIXME) dict<IdString, decltype(RTLIL::Cell::parameters)> erased_boxes; for (auto it = module->cells_.begin(); it != module->cells_.end(); ) { RTLIL::Cell* cell = it->second; @@ -518,6 +519,13 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri it = module->cells_.erase(it); continue; } + else if (cell->type.in("$_DFF_N_", "$_DFF_P_")) { + SigBit D = cell->getPort("\\D"); + SigBit Q = cell->getPort("\\Q"); + module->connect(Q, D); + it = module->cells_.erase(it); + continue; + } RTLIL::Module* box_module = design->module(cell->type); if (box_module && box_module->attributes.count("\\abc_box_id")) { erased_boxes.insert(std::make_pair(it->first, std::move(cell->parameters))); |