3 files changed, 92 insertions, 3 deletions

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 2d2ffa9a1..25d462ada 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -91,9 +91,16 @@ void rmunused_module_cells(Module *module, bool verbose)
 		Cell *cell = it.second;
 		for (auto &it2 : cell->connections()) {
 			if (!ct_all.cell_known(cell->type) || ct_all.cell_output(cell->type, it2.first))
-				for (auto bit : sigmap(it2.second))
+				for (auto raw_bit : it2.second) {
+					if (raw_bit.wire == nullptr)
+						continue;
+					auto bit = sigmap(raw_bit);
+					if (bit.wire == nullptr)
+						log_warning("Driver-driver conflict for %s between cell %s.%s and constant %s in %s: Resolved using constant.\n",
+								log_signal(raw_bit), log_id(cell), log_id(it2.first), log_signal(bit), log_id(module));
 					if (bit.wire != nullptr)
 						wire2driver[bit].insert(cell);
+				}
 		}
 		if (keep_cache.query(cell))
 			queue.insert(cell);
diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index 98653dc6b..f732baa17 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -322,6 +322,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 			}
 		}
 
+		SigSpec sig_q = sig;
 		ce.assign_map.apply(insig);
 		ce.assign_map.apply(rstval);
 		ce.assign_map.apply(sig);
@@ -350,13 +351,13 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 		else if (!rstval.is_fully_const() && !ce.eval(rstval))
 		{
 			log_warning("Async reset value `%s' is not constant!\n", log_signal(rstval));
-			gen_dffsr(mod, insig, rstval, sig,
+			gen_dffsr(mod, insig, rstval, sig_q,
 					sync_edge->type == RTLIL::SyncType::STp,
 					sync_level && sync_level->type == RTLIL::SyncType::ST1,
 					sync_edge->signal, sync_level->signal, proc);
 		}
 		else
-			gen_dff(mod, insig, rstval.as_const(), sig,
+			gen_dff(mod, insig, rstval.as_const(), sig_q,
 					sync_edge && sync_edge->type == RTLIL::SyncType::STp,
 					sync_level && sync_level->type == RTLIL::SyncType::ST1,
 					sync_edge ? sync_edge->signal : SigSpec(),
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc
index ef6d5dd72..d334cf7d9 100644
--- a/passes/sat/clk2fflogic.cc
+++ b/passes/sat/clk2fflogic.cc
@@ -72,6 +72,87 @@ struct Clk2fflogicPass : public Pass {
 
 			for (auto cell : vector<Cell*>(module->selected_cells()))
 			{
+				if (cell->type.in("$mem"))
+				{
+					int abits = cell->getParam("\\ABITS").as_int();
+					int width = cell->getParam("\\WIDTH").as_int();
+					int rd_ports = cell->getParam("\\RD_PORTS").as_int();
+					int wr_ports = cell->getParam("\\WR_PORTS").as_int();
+
+					for (int i = 0; i < rd_ports; i++) {
+						if (cell->getParam("\\RD_CLK_ENABLE").extract(i).as_bool())
+							log_error("Read port %d of memory %s.%s is clocked. This is not supported by \"clk2fflogic\"! "
+									"Call \"memory\" with -nordff to avoid this error.\n", i, log_id(cell), log_id(module));
+					}
+
+					Const wr_clk_en_param = cell->getParam("\\WR_CLK_ENABLE");
+					Const wr_clk_pol_param = cell->getParam("\\WR_CLK_POLARITY");
+
+					SigSpec wr_clk_port = cell->getPort("\\WR_CLK");
+					SigSpec wr_en_port = cell->getPort("\\WR_EN");
+					SigSpec wr_addr_port = cell->getPort("\\WR_ADDR");
+					SigSpec wr_data_port = cell->getPort("\\WR_DATA");
+
+					for (int wport = 0; wport < wr_ports; wport++)
+					{
+						bool clken = wr_clk_en_param[wport] == State::S1;
+						bool clkpol = wr_clk_pol_param[wport] == State::S1;
+
+						if (!clken)
+							continue;
+
+						SigBit clk = wr_clk_port[wport];
+						SigSpec en = wr_en_port.extract(wport*width, width);
+						SigSpec addr = wr_addr_port.extract(wport*abits, abits);
+						SigSpec data = wr_data_port.extract(wport*width, width);
+
+						log("Modifying write port %d on memory %s.%s: CLK=%s, A=%s, D=%s\n",
+								wport, log_id(module), log_id(cell), log_signal(clk),
+								log_signal(addr), log_signal(data));
+
+						Wire *past_clk = module->addWire(NEW_ID);
+						past_clk->attributes["\\init"] = clkpol ? State::S1 : State::S0;
+						module->addFf(NEW_ID, clk, past_clk);
+
+						SigSpec clock_edge_pattern;
+
+						if (clkpol) {
+							clock_edge_pattern.append_bit(State::S0);
+							clock_edge_pattern.append_bit(State::S1);
+						} else {
+							clock_edge_pattern.append_bit(State::S1);
+							clock_edge_pattern.append_bit(State::S0);
+						}
+
+						SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern);
+
+						SigSpec en_q = module->addWire(NEW_ID, GetSize(addr));
+						module->addFf(NEW_ID, en, en_q);
+
+						SigSpec addr_q = module->addWire(NEW_ID, GetSize(addr));
+						module->addFf(NEW_ID, addr, addr_q);
+
+						SigSpec data_q = module->addWire(NEW_ID, GetSize(data));
+						module->addFf(NEW_ID, data, data_q);
+
+						wr_clk_port[wport] = State::S0;
+						wr_en_port.replace(wport*width, module->Mux(NEW_ID, Const(0, GetSize(en_q)), en_q, clock_edge));
+						wr_addr_port.replace(wport*abits, addr_q);
+						wr_data_port.replace(wport*width, data_q);
+
+						wr_clk_en_param[wport] = State::S0;
+						wr_clk_pol_param[wport] = State::S0;
+					}
+
+					cell->setParam("\\WR_CLK_ENABLE", wr_clk_en_param);
+					cell->setParam("\\WR_CLK_POLARITY", wr_clk_pol_param);
+
+					cell->setPort("\\WR_CLK", wr_clk_port);
+					cell->setPort("\\WR_EN", wr_en_port);
+					cell->setPort("\\WR_ADDR", wr_addr_port);
+					cell->setPort("\\WR_DATA", wr_data_port);
+				}
+
 				if (cell->type.in("$dlatch"))
 				{
 					bool enpol = cell->parameters["\\EN_POLARITY"].as_bool();