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-rw-r--r--passes/pmgen/xilinx_srl.pmg12
1 files changed, 10 insertions, 2 deletions
diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg
index ae29ac6c9..cd7461052 100644
--- a/passes/pmgen/xilinx_srl.pmg
+++ b/passes/pmgen/xilinx_srl.pmg
@@ -10,6 +10,8 @@ endcode
match first
select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
+ select !first->get_bool_attribute(\keep)
+ select !port(first, \Q).as_wire()->get_bool_attribute(\keep)
filter !non_first_cells.count(first)
//generate
// SigSpec A = module->addWire(NEW_ID);
@@ -46,11 +48,15 @@ subpattern setup
match first
select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
+ select !first->get_bool_attribute(\keep)
+ select !port(first, \Q).as_wire()->get_bool_attribute(\keep)
endmatch
match next
- select nusers(port(next, \Q)) == 2
select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
+ select !next->get_bool_attribute(\keep)
+ select !port(next, \Q).as_wire()->get_bool_attribute(\keep)
+ select nusers(port(next, \Q)) == 2
index <IdString> next->type === first->type
index <SigSpec> port(next, \Q) === port(first, \D)
endmatch
@@ -66,8 +72,10 @@ arg first
match next
semioptional
- select nusers(port(next, \Q)) == 2
select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
+ select !next->get_bool_attribute(\keep)
+ select !port(next, \Q).as_wire()->get_bool_attribute(\keep)
+ select nusers(port(next, \Q)) == 2
index <IdString> next->type === chain.back()->type
index <SigSpec> port(next, \Q) === port(chain.back(), \D)
//generate 10