diff options
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/wreduce.cc | 2 | ||||
| -rw-r--r-- | passes/pmgen/.gitignore | 2 | ||||
| -rw-r--r-- | passes/pmgen/Makefile.inc | 13 | ||||
| -rw-r--r-- | passes/pmgen/README.md | 2 | ||||
| -rw-r--r-- | passes/pmgen/split_shiftx.cc | 78 | ||||
| -rw-r--r-- | passes/pmgen/split_shiftx.pmg | 56 |
6 files changed, 144 insertions, 9 deletions
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 52245ce3e..68e077cf9 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -462,12 +462,10 @@ struct WreduceWorker SigSpec initsig = init_attr_sigmap(w); int width = std::min(GetSize(initval), GetSize(initsig)); for (int i = 0; i < width; i++) { - log_dump(initsig[i], remove_init_bits.count(initsig[i])); if (!remove_init_bits.count(initsig[i])) new_initval[i] = initval[i]; } w->attributes.at("\\init") = new_initval; - log_dump(w->name, initval, new_initval); } } } diff --git a/passes/pmgen/.gitignore b/passes/pmgen/.gitignore index c9263057e..52dfd93f3 100644 --- a/passes/pmgen/.gitignore +++ b/passes/pmgen/.gitignore @@ -1 +1 @@ -/ice40_dsp_pm.h +*_pm.h diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc index e0609d9ba..5669bd3d1 100644 --- a/passes/pmgen/Makefile.inc +++ b/passes/pmgen/Makefile.inc @@ -1,8 +1,11 @@ -OBJS += passes/pmgen/ice40_dsp.o +PMG_SRC = $(wildcard passes/pmgen/*.pmg) +PMG_OBJS += $(patsubst %.pmg, %.o, $(PMG_SRC)) +OBJS += $(PMG_OBJS) -passes/pmgen/ice40_dsp.o: passes/pmgen/ice40_dsp_pm.h -EXTRA_OBJS += passes/pmgen/ice40_dsp_pm.h -.SECONDARY: passes/pmgen/ice40_dsp_pm.h +$(PMG_OBJS): %.o: %_pm.h -passes/pmgen/ice40_dsp_pm.h: passes/pmgen/pmgen.py passes/pmgen/ice40_dsp.pmg +EXTRA_OBJS += $(patsubst %.pmg, %_pm.h, $(PMG_SRC)) +.SECONDARY: $(EXTRA_OBJS) + +%_pm.h: passes/pmgen/pmgen.py %.pmg $(P) mkdir -p passes/pmgen && python3 $^ $@ diff --git a/passes/pmgen/README.md b/passes/pmgen/README.md index 7a46558b1..320e95a77 100644 --- a/passes/pmgen/README.md +++ b/passes/pmgen/README.md @@ -220,5 +220,5 @@ But in some cases it is more natural to utilize the implicit branch statement: portAB = \B; endcode -There is an implicit `code..endcode` block at the end of each `.pgm` file +There is an implicit `code..endcode` block at the end of each `.pmg` file that just accepts everything that gets all the way there. diff --git a/passes/pmgen/split_shiftx.cc b/passes/pmgen/split_shiftx.cc new file mode 100644 index 000000000..71fb4e9ef --- /dev/null +++ b/passes/pmgen/split_shiftx.cc @@ -0,0 +1,78 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" +#include "passes/pmgen/split_shiftx_pm.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +void create_split_shiftx(split_shiftx_pm &pm) +{ + if (pm.st.shiftxB.empty()) + return; + log_assert(pm.st.shiftx); + SigSpec A = pm.st.shiftx->getPort("\\A"); + SigSpec Y = pm.st.shiftx->getPort("\\Y"); + const int A_WIDTH = pm.st.shiftx->getParam("\\A_WIDTH").as_int(); + const int Y_WIDTH = pm.st.shiftx->getParam("\\Y_WIDTH").as_int(); + log_assert(Y_WIDTH > 1); + std::vector<SigBit> bits; + bits.resize(A_WIDTH / Y_WIDTH); + for (int i = 0; i < Y_WIDTH; ++i) { + for (int j = 0; j < A_WIDTH/Y_WIDTH; ++j) + bits[j] = A[j*Y_WIDTH + i]; + pm.module->addShiftx(NEW_ID, bits, pm.st.shiftxB, Y[i]); + } + pm.st.shiftx->unsetPort("\\Y"); + + pm.autoremove(pm.st.shiftx); + pm.autoremove(pm.st.macc); +} + +struct BitblastShiftxPass : public Pass { + BitblastShiftxPass() : Pass("split_shiftx", "Split up multi-bit $shiftx cells") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" split_shiftx [selection]\n"); + log("\n"); + log("Split up $shiftx cells where Y_WIDTH > 1, with consideration for any $macc\n"); + log("cells that may be driving their B inputs.\n"); + log("\n"); + } + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + { + log_header(design, "Executing SPLIT_SHIFTX pass.\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + break; + } + extra_args(args, argidx, design); + + for (auto module : design->selected_modules()) + split_shiftx_pm(module, module->selected_cells()).run(create_split_shiftx); + } +} BitblastShiftxPass; + +PRIVATE_NAMESPACE_END diff --git a/passes/pmgen/split_shiftx.pmg b/passes/pmgen/split_shiftx.pmg new file mode 100644 index 000000000..11b19bfe4 --- /dev/null +++ b/passes/pmgen/split_shiftx.pmg @@ -0,0 +1,56 @@ +state <SigSpec> shiftxB + +match shiftx + select shiftx->type == $shiftx + select param(shiftx, \Y_WIDTH).as_int() > 1 +endmatch + +code shiftxB + shiftxB = port(shiftx, \B); + const int b_width = param(shiftx, \B_WIDTH).as_int(); + if (param(shiftx, \B_SIGNED) != 0 && shiftxB[b_width-1] == RTLIL::S0) + shiftxB = shiftxB.extract(0, b_width-1); +endcode + +match macc + select macc->type == $macc + select param(macc, \B_WIDTH).as_int() == 0 + index <SigSpec> port(macc, \Y) === shiftxB + optional +endmatch + +code shiftxB + if (macc) { + Const config = param(macc, \CONFIG); + const int config_width = param(macc, \CONFIG_WIDTH).as_int(); + const int num_bits = config.extract(0, 4).as_int(); + const int num_ports = (config_width - 4) / (2 + 2*num_bits); + if (num_ports != 1) { + shiftxB = nullptr; + reject; + } + // IS_SIGNED? + if (config[4] == 1) { + shiftxB = nullptr; + reject; + } + // DO_SUBTRACT? + if (config[5] == 1) { + shiftxB = nullptr; + reject; + } + const int port_size_A = config.extract(6, num_bits).as_int(); + const int port_size_B = config.extract(6 + num_bits, num_bits).as_int(); + const SigSpec port_B = port(macc, \A).extract(port_size_A, port_size_B); + if (!port_B.is_fully_const()) { + shiftxB = nullptr; + reject; + } + const int multiply_factor = port_B.as_int(); + if (multiply_factor != param(shiftx, \Y_WIDTH).as_int()) { + shiftxB = nullptr; + reject; + } + shiftxB = port(macc, \A).extract(0, port_size_A); + } +endcode |