aboutsummaryrefslogtreecommitdiffstats
path: root/passes/tests
diff options
context:
space:
mode:
Diffstat (limited to 'passes/tests')
-rw-r--r--passes/tests/flowmap/flow.v22
-rw-r--r--passes/tests/flowmap/flowp.v16
-rw-r--r--passes/tests/flowmap/pack1.v11
-rw-r--r--passes/tests/flowmap/pack1p.v11
-rw-r--r--passes/tests/flowmap/pack2.v15
-rw-r--r--passes/tests/flowmap/pack2p.v15
-rw-r--r--passes/tests/flowmap/pack3.v15
-rw-r--r--passes/tests/flowmap/pack3p.v15
-rw-r--r--passes/tests/test_abcloop.cc4
-rw-r--r--passes/tests/test_autotb.cc7
-rw-r--r--passes/tests/test_cell.cc44
11 files changed, 149 insertions, 26 deletions
diff --git a/passes/tests/flowmap/flow.v b/passes/tests/flowmap/flow.v
new file mode 100644
index 000000000..297ef910e
--- /dev/null
+++ b/passes/tests/flowmap/flow.v
@@ -0,0 +1,22 @@
+// Exact reproduction of Figure 2(a) from 10.1109/43.273754.
+module top(...);
+ input a,b,c,d,e,f;
+ wire nA = b&c;
+ wire A = !nA;
+ wire nB = c|d;
+ wire B = !nB;
+ wire nC = e&f;
+ wire C = !nC;
+ wire D = A|B;
+ wire E = a&D;
+ wire nF = D&C;
+ wire F = !nF;
+ wire nG = F|B;
+ wire G = !nG;
+ wire H = a&F;
+ wire I = E|G;
+ wire J = G&C;
+ wire np = H&I;
+ output p = !np;
+ output q = A|J;
+endmodule
diff --git a/passes/tests/flowmap/flowp.v b/passes/tests/flowmap/flowp.v
new file mode 100644
index 000000000..2fb40ffa4
--- /dev/null
+++ b/passes/tests/flowmap/flowp.v
@@ -0,0 +1,16 @@
+// Like flow.v, but results in a network identical to Figure 2(b).
+module top(...);
+ input a,b,c,d,e,f;
+ wire A = b&c;
+ wire B = c|d;
+ wire C = e&f;
+ wire D = A|B;
+ wire E = a&D;
+ wire F = D&C;
+ wire G = F|B;
+ wire H = a&F;
+ wire I = E|G;
+ wire J = G&C;
+ output p = H&I;
+ output q = A|J;
+endmodule
diff --git a/passes/tests/flowmap/pack1.v b/passes/tests/flowmap/pack1.v
new file mode 100644
index 000000000..9454edf3c
--- /dev/null
+++ b/passes/tests/flowmap/pack1.v
@@ -0,0 +1,11 @@
+// Exact reproduction of Figure 3(a) from 10.1109/92.285741.
+module top(...);
+ input a,b,c,d,e,f,g,h;
+ wire x = !(c|d);
+ wire y = !(e&f);
+ wire u = !(a&b);
+ wire v = !(x|y);
+ wire w = !(g&h);
+ output s = !(u|v);
+ output t = !(v|w);
+endmodule
diff --git a/passes/tests/flowmap/pack1p.v b/passes/tests/flowmap/pack1p.v
new file mode 100644
index 000000000..fdb278833
--- /dev/null
+++ b/passes/tests/flowmap/pack1p.v
@@ -0,0 +1,11 @@
+// Like pack1.v, but results in a simpler network.
+module top(...);
+ input a,b,c,d,e,f,g,h;
+ wire x = c|d;
+ wire y = e&f;
+ wire u = a&b;
+ wire v = x|y;
+ wire w = g&h;
+ output s = u|v;
+ output t = v|w;
+endmodule
diff --git a/passes/tests/flowmap/pack2.v b/passes/tests/flowmap/pack2.v
new file mode 100644
index 000000000..445e4afb0
--- /dev/null
+++ b/passes/tests/flowmap/pack2.v
@@ -0,0 +1,15 @@
+// Exact reproduction of Figure 4(a) from 10.1109/92.285741.
+module top(...);
+ (* $flowmap_level=1 *) input a;
+ (* $flowmap_level=1 *) input b;
+ (* $flowmap_level=2 *) input c;
+ (* $flowmap_level=1 *) input d;
+ (* $flowmap_level=3 *) input e;
+ (* $flowmap_level=1 *) input f;
+ wire u = !(a&b);
+ wire w = !(c|d);
+ wire v = !(u|w);
+ wire n0 = !(w&e);
+ wire n1 = !(n0|f);
+ output n2 = !(v&n1);
+endmodule
diff --git a/passes/tests/flowmap/pack2p.v b/passes/tests/flowmap/pack2p.v
new file mode 100644
index 000000000..d4b41733d
--- /dev/null
+++ b/passes/tests/flowmap/pack2p.v
@@ -0,0 +1,15 @@
+// Like pack2.v, but results in a simpler network.
+module top(...);
+ (* $flowmap_level=1 *) input a;
+ (* $flowmap_level=1 *) input b;
+ (* $flowmap_level=2 *) input c;
+ (* $flowmap_level=1 *) input d;
+ (* $flowmap_level=3 *) input e;
+ (* $flowmap_level=1 *) input f;
+ wire u = a&b;
+ wire w = c|d;
+ wire v = u|w;
+ wire n0 = w&e;
+ wire n1 = n0|f;
+ output n2 = v&n1;
+endmodule
diff --git a/passes/tests/flowmap/pack3.v b/passes/tests/flowmap/pack3.v
new file mode 100644
index 000000000..06147a1aa
--- /dev/null
+++ b/passes/tests/flowmap/pack3.v
@@ -0,0 +1,15 @@
+// Exact reproduction of Figure 5(a) (bottom) from 10.1109/92.285741.
+module top(...);
+ input a,b,c,d,e,f,g,h,i,j;
+ wire x = !(a&b);
+ wire y = !(c|d);
+ wire z = !(e|f);
+ wire n0 = !(g&h);
+ wire n1 = !(i|j);
+ wire w = !(x&y);
+ wire n2 = !(z&n0);
+ wire n3 = !(n0|n1);
+ wire n4 = !(n2|n3);
+ wire v = !(w|n5);
+ output u = !(w&v);
+endmodule
diff --git a/passes/tests/flowmap/pack3p.v b/passes/tests/flowmap/pack3p.v
new file mode 100644
index 000000000..bc6ac1757
--- /dev/null
+++ b/passes/tests/flowmap/pack3p.v
@@ -0,0 +1,15 @@
+// Like pack2.v, but results in a simpler network.
+module top(...);
+ input a,b,c,d,e,f,g,h,i,j;
+ wire x = a&b;
+ wire y = c|d;
+ wire z = e|f;
+ wire n0 = g&h;
+ wire n1 = i|j;
+ wire w = x&y;
+ wire n2 = z&n0;
+ wire n3 = n0|n1;
+ wire n4 = n2|n3;
+ wire v = w|n5;
+ output u = w&v;
+endmodule
diff --git a/passes/tests/test_abcloop.cc b/passes/tests/test_abcloop.cc
index 09cb41954..5d5466afe 100644
--- a/passes/tests/test_abcloop.cc
+++ b/passes/tests/test_abcloop.cc
@@ -244,7 +244,7 @@ static void test_abcloop()
struct TestAbcloopPass : public Pass {
TestAbcloopPass() : Pass("test_abcloop", "automatically test handling of loops in abc command") { }
- virtual void help()
+ void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -259,7 +259,7 @@ struct TestAbcloopPass : public Pass {
log(" use this value as rng seed value (default = unix time).\n");
log("\n");
}
- virtual void execute(std::vector<std::string> args, RTLIL::Design*)
+ void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
{
int num_iter = 100;
xorshift32_state = 0;
diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc
index cb31056f4..a5ac3130f 100644
--- a/passes/tests/test_autotb.cc
+++ b/passes/tests/test_autotb.cc
@@ -324,7 +324,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s
struct TestAutotbBackend : public Backend {
TestAutotbBackend() : Backend("=test_autotb", "generate simple test benches") { }
- virtual void help()
+ void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -345,11 +345,14 @@ struct TestAutotbBackend : public Backend {
log("value after initialization. This can e.g. be used to force a reset signal\n");
log("low in order to explore more inner states in a state machine.\n");
log("\n");
+ log("The attribute 'gentb_skip' can be attached to modules to suppress testbench\n");
+ log("generation.\n");
+ log("\n");
log(" -n <int>\n");
log(" number of iterations the test bench should run (default = 1000)\n");
log("\n");
}
- virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+ void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
int num_iter = 1000;
int seed = 0;
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index 47b6bdf23..88116eeec 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -43,7 +43,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
RTLIL::Cell *cell = module->addCell("\\UUT", cell_type);
RTLIL::Wire *wire;
- if (cell_type == "$mux" || cell_type == "$pmux")
+ if (cell_type.in("$mux", "$pmux"))
{
int width = 1 + xorshift32(8);
int swidth = cell_type == "$mux" ? 1 : 1 + xorshift32(8);
@@ -186,7 +186,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
RTLIL::SigSpec config;
for (int i = 0; i < (1 << width); i++)
- config.append(xorshift32(2) ? RTLIL::S1 : RTLIL::S0);
+ config.append(xorshift32(2) ? State::S1 : State::S0);
cell->setParam("\\LUT", config.as_const());
}
@@ -209,16 +209,16 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
for (int i = 0; i < width*depth; i++)
switch (xorshift32(3)) {
case 0:
- config.append(RTLIL::S1);
- config.append(RTLIL::S0);
+ config.append(State::S1);
+ config.append(State::S0);
break;
case 1:
- config.append(RTLIL::S0);
- config.append(RTLIL::S1);
+ config.append(State::S0);
+ config.append(State::S1);
break;
case 2:
- config.append(RTLIL::S0);
- config.append(RTLIL::S0);
+ config.append(State::S0);
+ config.append(State::S0);
break;
}
@@ -264,7 +264,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
cell->setPort("\\Y", wire);
}
- if (muxdiv && (cell_type == "$div" || cell_type == "$mod")) {
+ if (muxdiv && cell_type.in("$div", "$mod")) {
auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort("\\B"));
auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort("\\Y")));
module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort("\\Y"));
@@ -308,18 +308,18 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
case 0:
n = xorshift32(GetSize(sig) + 1);
for (int i = 0; i < n; i++)
- sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0;
+ sig[i] = xorshift32(2) == 1 ? State::S1 : State::S0;
break;
case 1:
n = xorshift32(GetSize(sig) + 1);
for (int i = n; i < GetSize(sig); i++)
- sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0;
+ sig[i] = xorshift32(2) == 1 ? State::S1 : State::S0;
break;
case 2:
n = xorshift32(GetSize(sig));
m = xorshift32(GetSize(sig));
for (int i = min(n, m); i < max(n, m); i++)
- sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0;
+ sig[i] = xorshift32(2) == 1 ? State::S1 : State::S0;
break;
}
@@ -491,7 +491,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
RTLIL::Const in_value;
for (int i = 0; i < GetSize(gold_wire); i++)
- in_value.bits.push_back(xorshift32(2) ? RTLIL::S1 : RTLIL::S0);
+ in_value.bits.push_back(xorshift32(2) ? State::S1 : State::S0);
if (xorshift32(4) == 0) {
int inv_chance = 1 + xorshift32(8);
@@ -591,11 +591,11 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
}
for (int i = 0; i < GetSize(out_sig); i++) {
- if (out_val[i] != RTLIL::S0 && out_val[i] != RTLIL::S1)
+ if (out_val[i] != State::S0 && out_val[i] != State::S1)
continue;
- if (out_val[i] == RTLIL::S0 && sat1_model_value.at(i) == false)
+ if (out_val[i] == State::S0 && sat1_model_value.at(i) == false)
continue;
- if (out_val[i] == RTLIL::S1 && sat1_model_value.at(i) == true)
+ if (out_val[i] == State::S1 && sat1_model_value.at(i) == true)
continue;
log_error("Mismatch in sat model 1 (no undef modeling) output!\n");
}
@@ -627,12 +627,12 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
for (int i = 0; i < GetSize(out_sig); i++) {
if (sat2_model_value.at(GetSize(out_sig) + i)) {
- if (out_val[i] != RTLIL::S0 && out_val[i] != RTLIL::S1)
+ if (out_val[i] != State::S0 && out_val[i] != State::S1)
continue;
} else {
- if (out_val[i] == RTLIL::S0 && sat2_model_value.at(i) == false)
+ if (out_val[i] == State::S0 && sat2_model_value.at(i) == false)
continue;
- if (out_val[i] == RTLIL::S1 && sat2_model_value.at(i) == true)
+ if (out_val[i] == State::S1 && sat2_model_value.at(i) == true)
continue;
}
log_error("Mismatch in sat model 2 (undef modeling) output!\n");
@@ -652,7 +652,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
struct TestCellPass : public Pass {
TestCellPass() : Pass("test_cell", "automatically test the implementation of a cell type") { }
- virtual void help()
+ void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -712,7 +712,7 @@ struct TestCellPass : public Pass {
log(" create a Verilog test bench to test simlib and write_verilog\n");
log("\n");
}
- virtual void execute(std::vector<std::string> args, RTLIL::Design*)
+ void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
{
int num_iter = 100;
std::string techmap_cmd = "techmap -assert";
@@ -872,7 +872,7 @@ struct TestCellPass : public Pass {
continue;
}
- if (args[argidx].substr(0, 1) == "/") {
+ if (args[argidx].compare(0, 1, "/") == 0) {
std::vector<std::string> new_selected_cell_types;
for (auto it : selected_cell_types)
if (it != args[argidx].substr(1))
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-24 11:40:17 +0000