diff options
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/extract_reduce.cc | 2 | ||||
| -rw-r--r-- | passes/techmap/flowmap.cc | 2 | ||||
| -rw-r--r-- | passes/techmap/techmap.cc | 4 |
3 files changed, 4 insertions, 4 deletions
diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc index 11cfddcd9..92c52398c 100644 --- a/passes/techmap/extract_reduce.cc +++ b/passes/techmap/extract_reduce.cc @@ -286,7 +286,7 @@ struct ExtractReducePass : public Pass SigSpec input; for (auto b : input_pool) if (input_pool_intermed.count(b) == 0) - input.append_bit(b); + input.append(b); SigBit output = sigmap(head_cell->getPort(ID::Y)[0]); diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc index a2ad87f7d..427b72a6a 100644 --- a/passes/techmap/flowmap.cc +++ b/passes/techmap/flowmap.cc @@ -1405,7 +1405,7 @@ struct FlowmapWorker RTLIL::SigSpec lut_a, lut_y = node; for (auto input_node : input_nodes) - lut_a.append_bit(input_node); + lut_a.append(input_node); lut_a.append(RTLIL::Const(State::Sx, minlut - input_nodes.size())); RTLIL::Cell *lut = module->addLut(NEW_ID, lut_a, lut_y, lut_table); diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 10001baaa..0a67d9dbe 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -906,8 +906,8 @@ struct TechmapWorker RTLIL::SigSig port_conn; for (auto &it : port_connmap) { - port_conn.first.append_bit(it.first); - port_conn.second.append_bit(it.second); + port_conn.first.append(it.first); + port_conn.second.append(it.second); } tpl->connect(port_conn); |