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-rw-r--r--passes/proc/proc_arst.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index 565d86a72..63d04d351 100644
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -33,7 +33,7 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp
if (signal == ref)
return true;
- for (auto &cell_it : mod->cells) {
+ for (auto &cell_it : mod->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == "$reduce_or" && cell->get("\\Y") == signal)
return check_signal(mod, cell->get("\\A"), ref, polarity);