diff options
Diffstat (limited to 'passes/opt')
-rw-r--r-- | passes/opt/opt_const.cc | 10 | ||||
-rw-r--r-- | passes/opt/share.cc | 1 | ||||
-rw-r--r-- | passes/opt/wreduce.cc | 6 |
3 files changed, 7 insertions, 10 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index ad6961872..d315dba35 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -181,7 +181,7 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com log("\n"); } - cover_list("opt.opt_const.fine.group", "$not", "$pos", "$bu0", "$and", "$or", "$xor", "$xnor", cell->type.str()); + cover_list("opt.opt_const.fine.group", "$not", "$pos", "$and", "$or", "$xor", "$xnor", cell->type.str()); module->remove(cell); did_something = true; @@ -236,7 +236,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (do_fine) { - if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$bu0" || + if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor") if (group_cell_inputs(module, cell, true, cell->type != "$pos", assign_map)) goto next_cell; @@ -586,7 +586,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (!keepdc) { - bool identity_bu0 = false; bool identity_wrt_a = false; bool identity_wrt_b = false; @@ -607,7 +606,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo RTLIL::SigSpec b = assign_map(cell->getPort("\\B")); if (b.is_fully_const() && b.as_bool() == false) - identity_wrt_a = true, identity_bu0 = true; + identity_wrt_a = true; } if (cell->type == "$mul") @@ -646,7 +645,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->parameters.at("\\A_SIGNED") = cell->parameters.at("\\B_SIGNED"); } - cell->type = identity_bu0 ? "$bu0" : "$pos"; + cell->type = "$pos"; cell->unsetPort("\\B"); cell->parameters.erase("\\B_WIDTH"); cell->parameters.erase("\\B_SIGNED"); @@ -840,7 +839,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo FOLD_2ARG_CELL(pow) FOLD_1ARG_CELL(pos) - FOLD_1ARG_CELL(bu0) FOLD_1ARG_CELL(neg) // be very conservative with optimizing $mux cells as we do not want to break mux trees diff --git a/passes/opt/share.cc b/passes/opt/share.cc index 5f3cf4214..c372ed78a 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -923,7 +923,6 @@ struct SharePass : public Pass { config.generic_uni_ops.insert("$not"); // config.generic_uni_ops.insert("$pos"); - // config.generic_uni_ops.insert("$bu0"); config.generic_uni_ops.insert("$neg"); config.generic_cbin_ops.insert("$and"); diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 2269859d1..321a1aa55 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -37,7 +37,7 @@ struct WreduceConfig WreduceConfig() { - supported_cell_types << "$not" << "$pos" << "$bu0" << "$neg"; + supported_cell_types << "$not" << "$pos" << "$neg"; supported_cell_types << "$and" << "$or" << "$xor" << "$xnor"; supported_cell_types << "$shl" << "$shr" << "$sshl" << "$sshr" << "$shift" << "$shiftx"; supported_cell_types << "$lt" << "$le" << "$eq" << "$ne" << "$eqx" << "$nex" << "$ge" << "$gt"; @@ -181,7 +181,7 @@ struct WreduceWorker int max_port_a_size = cell->hasPort("\\A") ? SIZE(cell->getPort("\\A")) : -1; int max_port_b_size = cell->hasPort("\\B") ? SIZE(cell->getPort("\\B")) : -1; - if (cell->type.in("$not", "$pos", "$bu0", "$neg", "$and", "$or", "$xor", "$add", "$sub")) { + if (cell->type.in("$not", "$pos", "$neg", "$and", "$or", "$xor", "$add", "$sub")) { max_port_a_size = std::min(max_port_a_size, SIZE(cell->getPort("\\Y"))); max_port_b_size = std::min(max_port_b_size, SIZE(cell->getPort("\\Y"))); } @@ -216,7 +216,7 @@ struct WreduceWorker } } - if (cell->type.in("$pos", "$bu0", "$add", "$mul", "$and", "$or", "$xor")) + if (cell->type.in("$pos", "$add", "$mul", "$and", "$or", "$xor")) { bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); |