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-rw-r--r--passes/equiv/equiv_induct.cc16
-rw-r--r--passes/equiv/equiv_mark.cc8
-rw-r--r--passes/equiv/equiv_miter.cc12
-rw-r--r--passes/equiv/equiv_purge.cc10
-rw-r--r--passes/equiv/equiv_remove.cc6
-rw-r--r--passes/equiv/equiv_simple.cc16
-rw-r--r--passes/equiv/equiv_status.cc4
-rw-r--r--passes/equiv/equiv_struct.cc10
8 files changed, 41 insertions, 41 deletions
diff --git a/passes/equiv/equiv_induct.cc b/passes/equiv/equiv_induct.cc
index bcc68d6d2..77eec7490 100644
--- a/passes/equiv/equiv_induct.cc
+++ b/passes/equiv/equiv_induct.cc
@@ -59,8 +59,8 @@ struct EquivInductWorker
cell_warn_cache.insert(cell);
}
if (cell->type == "$equiv") {
- SigBit bit_a = sigmap(cell->getPort("\\A")).as_bit();
- SigBit bit_b = sigmap(cell->getPort("\\B")).as_bit();
+ SigBit bit_a = sigmap(cell->getPort(ID::A)).as_bit();
+ SigBit bit_b = sigmap(cell->getPort(ID::B)).as_bit();
if (bit_a != bit_b) {
int ez_a = satgen.importSigBit(bit_a, step);
int ez_b = satgen.importSigBit(bit_b, step);
@@ -125,7 +125,7 @@ struct EquivInductWorker
if (!ez->solve(new_step_not_consistent)) {
log(" Proof for induction step holds. Entire workset of %d cells proven!\n", GetSize(workset));
for (auto cell : workset)
- cell->setPort("\\B", cell->getPort("\\A"));
+ cell->setPort(ID::B, cell->getPort(ID::A));
success_counter += GetSize(workset);
return;
}
@@ -137,10 +137,10 @@ struct EquivInductWorker
for (auto cell : workset)
{
- SigBit bit_a = sigmap(cell->getPort("\\A")).as_bit();
- SigBit bit_b = sigmap(cell->getPort("\\B")).as_bit();
+ SigBit bit_a = sigmap(cell->getPort(ID::A)).as_bit();
+ SigBit bit_b = sigmap(cell->getPort(ID::B)).as_bit();
- log(" Trying to prove $equiv for %s:", log_signal(sigmap(cell->getPort("\\Y"))));
+ log(" Trying to prove $equiv for %s:", log_signal(sigmap(cell->getPort(ID::Y))));
int ez_a = satgen.importSigBit(bit_a, max_seq+1);
int ez_b = satgen.importSigBit(bit_b, max_seq+1);
@@ -151,7 +151,7 @@ struct EquivInductWorker
if (!ez->solve(cond)) {
log(" success!\n");
- cell->setPort("\\B", cell->getPort("\\A"));
+ cell->setPort(ID::B, cell->getPort(ID::A));
success_counter++;
} else {
log(" failed.\n");
@@ -220,7 +220,7 @@ struct EquivInductPass : public Pass {
for (auto cell : module->selected_cells())
if (cell->type == "$equiv") {
- if (cell->getPort("\\A") != cell->getPort("\\B"))
+ if (cell->getPort(ID::A) != cell->getPort(ID::B))
unproven_equiv_cells.insert(cell);
}
diff --git a/passes/equiv/equiv_mark.cc b/passes/equiv/equiv_mark.cc
index 135eaf145..b4d1d7871 100644
--- a/passes/equiv/equiv_mark.cc
+++ b/passes/equiv/equiv_mark.cc
@@ -122,8 +122,8 @@ struct EquivMarkWorker
{
auto cell = module->cell(cell_name);
- SigSpec sig_a = sigmap(cell->getPort("\\A"));
- SigSpec sig_b = sigmap(cell->getPort("\\B"));
+ SigSpec sig_a = sigmap(cell->getPort(ID::A));
+ SigSpec sig_b = sigmap(cell->getPort(ID::B));
if (sig_a == sig_b) {
for (auto bit : sig_a)
@@ -142,8 +142,8 @@ struct EquivMarkWorker
if (cell_regions.count(cell->name) || cell->type != "$equiv")
continue;
- SigSpec sig_a = sigmap(cell->getPort("\\A"));
- SigSpec sig_b = sigmap(cell->getPort("\\B"));
+ SigSpec sig_a = sigmap(cell->getPort(ID::A));
+ SigSpec sig_b = sigmap(cell->getPort(ID::B));
log_assert(sig_a != sig_b);
diff --git a/passes/equiv/equiv_miter.cc b/passes/equiv/equiv_miter.cc
index e06f9515b..5fd7c5418 100644
--- a/passes/equiv/equiv_miter.cc
+++ b/passes/equiv/equiv_miter.cc
@@ -57,7 +57,7 @@ struct EquivMiterWorker
for (auto &conn : c->connections()) {
if (!ct.cell_input(c->type, conn.first))
continue;
- if (c->type == "$equiv" && (conn.first == "\\A") != gold_mode)
+ if (c->type == "$equiv" && (conn.first == ID::A) != gold_mode)
continue;
for (auto bit : sigmap(conn.second))
if (bit_to_driver.count(bit))
@@ -213,18 +213,18 @@ struct EquivMiterWorker
vector<Cell*> equiv_cells;
for (auto c : miter_module->cells())
- if (c->type == "$equiv" && c->getPort("\\A") != c->getPort("\\B"))
+ if (c->type == "$equiv" && c->getPort(ID::A) != c->getPort(ID::B))
equiv_cells.push_back(c);
for (auto c : equiv_cells)
{
SigSpec cmp = mode_undef ?
- miter_module->LogicOr(NEW_ID, miter_module->Eqx(NEW_ID, c->getPort("\\A"), State::Sx),
- miter_module->Eqx(NEW_ID, c->getPort("\\A"), c->getPort("\\B"))) :
- miter_module->Eq(NEW_ID, c->getPort("\\A"), c->getPort("\\B"));
+ miter_module->LogicOr(NEW_ID, miter_module->Eqx(NEW_ID, c->getPort(ID::A), State::Sx),
+ miter_module->Eqx(NEW_ID, c->getPort(ID::A), c->getPort(ID::B))) :
+ miter_module->Eq(NEW_ID, c->getPort(ID::A), c->getPort(ID::B));
if (mode_cmp) {
- string cmp_name = string("\\cmp") + log_signal(c->getPort("\\Y"));
+ string cmp_name = string("\\cmp") + log_signal(c->getPort(ID::Y));
for (int i = 1; i < GetSize(cmp_name); i++)
if (cmp_name[i] == '\\')
cmp_name[i] = '_';
diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc
index 18b3e7d36..2a339682a 100644
--- a/passes/equiv/equiv_purge.cc
+++ b/passes/equiv/equiv_purge.cc
@@ -114,9 +114,9 @@ struct EquivPurgeWorker
continue;
}
- SigSpec sig_a = sigmap(cell->getPort("\\A"));
- SigSpec sig_b = sigmap(cell->getPort("\\B"));
- SigSpec sig_y = sigmap(cell->getPort("\\Y"));
+ SigSpec sig_a = sigmap(cell->getPort(ID::A));
+ SigSpec sig_b = sigmap(cell->getPort(ID::B));
+ SigSpec sig_y = sigmap(cell->getPort(ID::Y));
if (sig_a == sig_b)
continue;
@@ -130,7 +130,7 @@ struct EquivPurgeWorker
for (auto bit : sig_y)
visited.insert(bit);
- cell->setPort("\\Y", make_output(sig_y, cell->name));
+ cell->setPort(ID::Y, make_output(sig_y, cell->name));
}
SigSpec srcsig;
@@ -168,7 +168,7 @@ struct EquivPurgeWorker
for (auto cell : module->cells())
if (cell->type == "$equiv")
- cell->setPort("\\Y", rewrite_sigmap(sigmap(cell->getPort("\\Y"))));
+ cell->setPort(ID::Y, rewrite_sigmap(sigmap(cell->getPort(ID::Y))));
module->fixup_ports();
}
diff --git a/passes/equiv/equiv_remove.cc b/passes/equiv/equiv_remove.cc
index c5c28c7d9..2a78e5246 100644
--- a/passes/equiv/equiv_remove.cc
+++ b/passes/equiv/equiv_remove.cc
@@ -68,9 +68,9 @@ struct EquivRemovePass : public Pass {
for (auto module : design->selected_modules())
{
for (auto cell : module->selected_cells())
- if (cell->type == "$equiv" && (mode_gold || mode_gate || cell->getPort("\\A") == cell->getPort("\\B"))) {
- log("Removing $equiv cell %s.%s (%s).\n", log_id(module), log_id(cell), log_signal(cell->getPort("\\Y")));
- module->connect(cell->getPort("\\Y"), mode_gate ? cell->getPort("\\B") : cell->getPort("\\A"));
+ if (cell->type == "$equiv" && (mode_gold || mode_gate || cell->getPort(ID::A) == cell->getPort(ID::B))) {
+ log("Removing $equiv cell %s.%s (%s).\n", log_id(module), log_id(cell), log_signal(cell->getPort(ID::Y)));
+ module->connect(cell->getPort(ID::Y), mode_gate ? cell->getPort(ID::B) : cell->getPort(ID::A));
module->remove(cell);
remove_count++;
}
diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc
index c2fab26f2..0e5348880 100644
--- a/passes/equiv/equiv_simple.cc
+++ b/passes/equiv/equiv_simple.cc
@@ -90,8 +90,8 @@ struct EquivSimpleWorker
bool run_cell()
{
- SigBit bit_a = sigmap(equiv_cell->getPort("\\A")).as_bit();
- SigBit bit_b = sigmap(equiv_cell->getPort("\\B")).as_bit();
+ SigBit bit_a = sigmap(equiv_cell->getPort(ID::A)).as_bit();
+ SigBit bit_b = sigmap(equiv_cell->getPort(ID::B)).as_bit();
int ez_context = ez->frozen_literal();
if (satgen.model_undef)
@@ -115,9 +115,9 @@ struct EquivSimpleWorker
if (verbose) {
log(" Trying to prove $equiv cell %s:\n", log_id(equiv_cell));
- log(" A = %s, B = %s, Y = %s\n", log_signal(bit_a), log_signal(bit_b), log_signal(equiv_cell->getPort("\\Y")));
+ log(" A = %s, B = %s, Y = %s\n", log_signal(bit_a), log_signal(bit_b), log_signal(equiv_cell->getPort(ID::Y)));
} else {
- log(" Trying to prove $equiv for %s:", log_signal(equiv_cell->getPort("\\Y")));
+ log(" Trying to prove $equiv for %s:", log_signal(equiv_cell->getPort(ID::Y)));
}
int step = max_seq;
@@ -199,7 +199,7 @@ struct EquivSimpleWorker
if (!ez->solve(ez_context)) {
log(verbose ? " Proved equivalence! Marking $equiv cell as proven.\n" : " success!\n");
- equiv_cell->setPort("\\B", equiv_cell->getPort("\\A"));
+ equiv_cell->setPort(ID::B, equiv_cell->getPort(ID::A));
ez->assume(ez->NOT(ez_context));
return true;
}
@@ -256,7 +256,7 @@ struct EquivSimpleWorker
if (GetSize(equiv_cells) > 1) {
SigSpec sig;
for (auto c : equiv_cells)
- sig.append(sigmap(c->getPort("\\Y")));
+ sig.append(sigmap(c->getPort(ID::Y)));
log(" Grouping SAT models for %s:\n", log_signal(sig));
}
@@ -344,8 +344,8 @@ struct EquivSimplePass : public Pass {
int unproven_cells_counter = 0;
for (auto cell : module->selected_cells())
- if (cell->type == "$equiv" && cell->getPort("\\A") != cell->getPort("\\B")) {
- auto bit = sigmap(cell->getPort("\\Y").as_bit());
+ if (cell->type == "$equiv" && cell->getPort(ID::A) != cell->getPort(ID::B)) {
+ auto bit = sigmap(cell->getPort(ID::Y).as_bit());
auto bit_group = bit;
if (!nogroup && bit_group.wire)
bit_group.offset = 0;
diff --git a/passes/equiv/equiv_status.cc b/passes/equiv/equiv_status.cc
index b4a93ccf5..ac3af59f6 100644
--- a/passes/equiv/equiv_status.cc
+++ b/passes/equiv/equiv_status.cc
@@ -60,7 +60,7 @@ struct EquivStatusPass : public Pass {
for (auto cell : module->selected_cells())
if (cell->type == "$equiv") {
- if (cell->getPort("\\A") != cell->getPort("\\B"))
+ if (cell->getPort(ID::A) != cell->getPort(ID::B))
unproven_equiv_cells.push_back(cell);
else
proven_equiv_cells++;
@@ -77,7 +77,7 @@ struct EquivStatusPass : public Pass {
log(" Equivalence successfully proven!\n");
} else {
for (auto cell : unproven_equiv_cells)
- log(" Unproven $equiv %s: %s %s\n", log_id(cell), log_signal(cell->getPort("\\A")), log_signal(cell->getPort("\\B")));
+ log(" Unproven $equiv %s: %s %s\n", log_id(cell), log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)));
}
unproven_count += GetSize(unproven_equiv_cells);
diff --git a/passes/equiv/equiv_struct.cc b/passes/equiv/equiv_struct.cc
index 6672948b9..ba1fd1d26 100644
--- a/passes/equiv/equiv_struct.cc
+++ b/passes/equiv/equiv_struct.cc
@@ -127,8 +127,8 @@ struct EquivStructWorker
for (auto cell : module->selected_cells())
if (cell->type == "$equiv") {
- SigBit sig_a = sigmap(cell->getPort("\\A").as_bit());
- SigBit sig_b = sigmap(cell->getPort("\\B").as_bit());
+ SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit());
+ SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit());
equiv_bits.add(sig_b, sig_a);
equiv_inputs.insert(sig_a);
equiv_inputs.insert(sig_b);
@@ -140,9 +140,9 @@ struct EquivStructWorker
for (auto cell : module->selected_cells())
if (cell->type == "$equiv") {
- SigBit sig_a = sigmap(cell->getPort("\\A").as_bit());
- SigBit sig_b = sigmap(cell->getPort("\\B").as_bit());
- SigBit sig_y = sigmap(cell->getPort("\\Y").as_bit());
+ SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit());
+ SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit());
+ SigBit sig_y = sigmap(cell->getPort(ID::Y).as_bit());
if (sig_a == sig_b && equiv_inputs.count(sig_y)) {
log(" Purging redundant $equiv cell %s.\n", log_id(cell));
module->connect(sig_y, sig_a);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 00:14:13 +0000