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-rw-r--r--passes/cmds/design.cc84
1 files changed, 49 insertions, 35 deletions
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc
index 172addcc1..4612760cc 100644
--- a/passes/cmds/design.cc
+++ b/passes/cmds/design.cc
@@ -18,6 +18,7 @@
*/
#include "kernel/yosys.h"
+#include "frontends/verilog/preproc.h"
#include "frontends/ast/ast.h"
YOSYS_NAMESPACE_BEGIN
@@ -59,6 +60,11 @@ struct DesignPass : public Pass {
log("Push the current design to the stack and then clear the current design.\n");
log("\n");
log("\n");
+ log(" design -push-copy\n");
+ log("\n");
+ log("Push the current design to the stack without clearing the current design.\n");
+ log("\n");
+ log("\n");
log(" design -pop\n");
log("\n");
log("Reset the current design and pop the last design from the stack.\n");
@@ -100,6 +106,7 @@ struct DesignPass : public Pass {
bool reset_mode = false;
bool reset_vlog_mode = false;
bool push_mode = false;
+ bool push_copy_mode = false;
bool pop_mode = false;
bool import_mode = false;
RTLIL::Design *copy_from_design = NULL, *copy_to_design = NULL;
@@ -125,6 +132,11 @@ struct DesignPass : public Pass {
push_mode = true;
continue;
}
+ if (!got_mode && args[argidx] == "-push-copy") {
+ got_mode = true;
+ push_copy_mode = true;
+ continue;
+ }
if (!got_mode && args[argidx] == "-pop") {
got_mode = true;
pop_mode = true;
@@ -194,19 +206,19 @@ struct DesignPass : public Pass {
argidx = args.size();
}
- for (auto &it : copy_from_design->modules_) {
- if (sel.selected_whole_module(it.first)) {
- copy_src_modules.push_back(it.second);
+ for (auto mod : copy_from_design->modules()) {
+ if (sel.selected_whole_module(mod->name)) {
+ copy_src_modules.push_back(mod);
continue;
}
- if (sel.selected_module(it.first))
- log_cmd_error("Module %s is only partly selected.\n", RTLIL::id2cstr(it.first));
+ if (sel.selected_module(mod->name))
+ log_cmd_error("Module %s is only partly selected.\n", log_id(mod->name));
}
if (import_mode) {
for (auto module : copy_src_modules)
{
- if (module->get_bool_attribute("\\top")) {
+ if (module->get_bool_attribute(ID::top)) {
copy_src_modules.clear();
copy_src_modules.push_back(module);
break;
@@ -230,8 +242,8 @@ struct DesignPass : public Pass {
pool<Module*> queue;
dict<IdString, IdString> done;
- if (copy_to_design->modules_.count(prefix))
- delete copy_to_design->modules_.at(prefix);
+ if (copy_to_design->module(prefix) != nullptr)
+ copy_to_design->remove(copy_to_design->module(prefix));
if (GetSize(copy_src_modules) != 1)
log_cmd_error("No top module found in source design.\n");
@@ -240,12 +252,13 @@ struct DesignPass : public Pass {
{
log("Importing %s as %s.\n", log_id(mod), log_id(prefix));
- copy_to_design->modules_[prefix] = mod->clone();
- copy_to_design->modules_[prefix]->name = prefix;
- copy_to_design->modules_[prefix]->design = copy_to_design;
- copy_to_design->modules_[prefix]->attributes.erase("\\top");
+ RTLIL::Module *t = mod->clone();
+ t->name = prefix;
+ t->design = copy_to_design;
+ t->attributes.erase(ID::top);
+ copy_to_design->add(t);
- queue.insert(copy_to_design->modules_[prefix]);
+ queue.insert(t);
done[mod->name] = prefix;
}
@@ -268,15 +281,16 @@ struct DesignPass : public Pass {
log("Importing %s as %s.\n", log_id(fmod), log_id(trg_name));
- if (copy_to_design->modules_.count(trg_name))
- delete copy_to_design->modules_.at(trg_name);
+ if (copy_to_design->module(trg_name) != nullptr)
+ copy_to_design->remove(copy_to_design->module(trg_name));
- copy_to_design->modules_[trg_name] = fmod->clone();
- copy_to_design->modules_[trg_name]->name = trg_name;
- copy_to_design->modules_[trg_name]->design = copy_to_design;
- copy_to_design->modules_[trg_name]->attributes.erase("\\top");
+ RTLIL::Module *t = fmod->clone();
+ t->name = trg_name;
+ t->design = copy_to_design;
+ t->attributes.erase(ID::top);
+ copy_to_design->add(t);
- queue.insert(copy_to_design->modules_[trg_name]);
+ queue.insert(t);
done[cell->type] = trg_name;
}
@@ -294,21 +308,22 @@ struct DesignPass : public Pass {
{
std::string trg_name = as_name.empty() ? mod->name.str() : RTLIL::escape_id(as_name);
- if (copy_to_design->modules_.count(trg_name))
- delete copy_to_design->modules_.at(trg_name);
+ if (copy_to_design->module(trg_name) != nullptr)
+ copy_to_design->remove(copy_to_design->module(trg_name));
- copy_to_design->modules_[trg_name] = mod->clone();
- copy_to_design->modules_[trg_name]->name = trg_name;
- copy_to_design->modules_[trg_name]->design = copy_to_design;
+ RTLIL::Module *t = mod->clone();
+ t->name = trg_name;
+ t->design = copy_to_design;
+ copy_to_design->add(t);
}
}
- if (!save_name.empty() || push_mode)
+ if (!save_name.empty() || push_mode || push_copy_mode)
{
RTLIL::Design *design_copy = new RTLIL::Design;
- for (auto &it : design->modules_)
- design_copy->add(it.second->clone());
+ for (auto mod : design->modules())
+ design_copy->add(mod->clone());
design_copy->selection_stack = design->selection_stack;
design_copy->selection_vars = design->selection_vars;
@@ -317,7 +332,7 @@ struct DesignPass : public Pass {
if (saved_designs.count(save_name))
delete saved_designs.at(save_name);
- if (push_mode)
+ if (push_mode || push_copy_mode)
pushed_designs.push_back(design_copy);
else
saved_designs[save_name] = design_copy;
@@ -325,9 +340,8 @@ struct DesignPass : public Pass {
if (reset_mode || !load_name.empty() || push_mode || pop_mode)
{
- for (auto &it : design->modules_)
- delete it.second;
- design->modules_.clear();
+ for (auto mod : design->modules())
+ design->remove(mod);
design->selection_stack.clear();
design->selection_vars.clear();
@@ -346,15 +360,15 @@ struct DesignPass : public Pass {
delete node;
design->verilog_globals.clear();
- design->verilog_defines.clear();
+ design->verilog_defines->clear();
}
if (!load_name.empty() || pop_mode)
{
RTLIL::Design *saved_design = pop_mode ? pushed_designs.back() : saved_designs.at(load_name);
- for (auto &it : saved_design->modules_)
- design->add(it.second->clone());
+ for (auto mod : saved_design->modules())
+ design->add(mod->clone());
design->selection_stack = saved_design->selection_stack;
design->selection_vars = saved_design->selection_vars;
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-13 20:59:55 +0000