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-rw-r--r--frontends/ast/ast.cc1
-rw-r--r--frontends/ast/ast.h2
-rw-r--r--frontends/ast/genrtlil.cc27
-rw-r--r--frontends/ast/simplify.cc67
-rw-r--r--frontends/verific/verific.cc2
-rw-r--r--frontends/verilog/preproc.cc1
-rw-r--r--frontends/verilog/verilog_frontend.cc3
-rw-r--r--frontends/verilog/verilog_parser.y10
8 files changed, 100 insertions, 13 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index c8183580b..1c0a8b34d 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -1511,6 +1511,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
}
} else {
+ modname = new_modname;
log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
}
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 1b8ed22ca..907392166 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -250,6 +250,7 @@ namespace AST
// simplify() creates a simpler AST by unrolling for-loops, expanding generate blocks, etc.
// it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL()
bool simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int width_hint, bool sign_hint, bool in_param);
+ void replace_result_wire_name_in_function(const std::string &from, const std::string &to);
AstNode *readmem(bool is_readmemh, std::string mem_filename, AstNode *memory, int start_addr, int finish_addr, bool unconditional_init);
void expand_genblock(std::string index_var, std::string prefix, std::map<std::string, std::string> &name_map, bool original_scope = true);
void replace_ids(const std::string &prefix, const std::map<std::string, std::string> &rules);
@@ -264,6 +265,7 @@ namespace AST
// additional functionality for evaluating constant functions
struct varinfo_t { RTLIL::Const val; int offset; bool is_signed; };
bool has_const_only_constructs(bool &recommend_const_eval);
+ bool has_const_only_constructs(std::set<std::string>& visited, bool &recommend_const_eval);
void replace_variables(std::map<std::string, varinfo_t> &variables, AstNode *fcall);
AstNode *eval_const_function(AstNode *fcall);
bool is_simple_const_expr();
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index e878d0dd2..b8bfdf65e 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -106,6 +106,7 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column);
+ wire->is_signed = that->is_signed;
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
@@ -140,6 +141,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());
wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column);
+ wire->is_signed = that->is_signed;
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
@@ -1721,8 +1723,29 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
if (child->type == AST_ARGUMENT) {
RTLIL::SigSpec sig;
- if (child->children.size() > 0)
- sig = child->children[0]->genRTLIL();
+ if (child->children.size() > 0) {
+ AstNode *arg = child->children[0];
+ int local_width_hint = -1;
+ bool local_sign_hint = false;
+ // don't inadvertently attempt to detect the width of interfaces
+ if (arg->type != AST_IDENTIFIER || !arg->id2ast || arg->id2ast->type != AST_CELL)
+ arg->detectSignWidth(local_width_hint, local_sign_hint);
+ sig = arg->genRTLIL(local_width_hint, local_sign_hint);
+ log_assert(local_sign_hint == arg->is_signed);
+ if (sig.is_wire()) {
+ // if the resulting SigSpec is a wire, its
+ // signedness should match that of the AstNode
+ log_assert(arg->is_signed == sig.as_wire()->is_signed);
+ } else if (arg->is_signed) {
+ // non-trivial signed nodes are indirected through
+ // signed wires to enable sign extension
+ RTLIL::IdString wire_name = NEW_ID;
+ RTLIL::Wire *wire = current_module->addWire(wire_name, arg->bits.size());
+ wire->is_signed = true;
+ current_module->connect(wire, sig);
+ sig = wire;
+ }
+ }
if (child->str.size() == 0) {
char buf[100];
snprintf(buf, 100, "$%d", ++port_counter);
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index fb6623f02..d4242f1e7 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1205,6 +1205,11 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
current_block = this;
current_block_child = children[i];
}
+ if (!in_param_here && type == AST_FCALL) {
+ bool recommend_const_eval = false;
+ bool require_const_eval = has_const_only_constructs(recommend_const_eval);
+ in_param_here = recommend_const_eval || require_const_eval;
+ }
if ((type == AST_ALWAYS || type == AST_INITIAL) && children[i]->type == AST_BLOCK)
current_top_block = children[i];
if (i == 0 && child_0_is_self_determined)
@@ -3170,6 +3175,8 @@ skip_dynamic_range_lvalue_expansion:;
if (all_args_const) {
AstNode *func_workspace = current_scope[str]->clone();
+ func_workspace->str = NEW_ID.str();
+ func_workspace->replace_result_wire_name_in_function(str, func_workspace->str);
newNode = func_workspace->eval_const_function(this);
delete func_workspace;
goto apply_newNode;
@@ -3337,6 +3344,25 @@ skip_dynamic_range_lvalue_expansion:;
wire->type = AST_LOCALPARAM;
wire->attributes.erase(ID::nosync);
wire->children.insert(wire->children.begin(), arg->clone());
+ // args without a range implicitly have width 1
+ if (wire->children.back()->type != AST_RANGE) {
+ // check if this wire is redeclared with an explicit size
+ bool uses_explicit_size = false;
+ for (const AstNode *other_child : decl->children)
+ if (other_child->type == AST_WIRE && child->str == other_child->str
+ && !other_child->children.empty()
+ && other_child->children.back()->type == AST_RANGE) {
+ uses_explicit_size = true;
+ break;
+ }
+ if (!uses_explicit_size) {
+ AstNode* range = new AstNode();
+ range->type = AST_RANGE;
+ wire->children.push_back(range);
+ range->children.push_back(mkconst_int(0, true));
+ range->children.push_back(mkconst_int(0, true));
+ }
+ }
continue;
}
AstNode *wire_id = new AstNode(AST_IDENTIFIER);
@@ -3427,7 +3453,14 @@ replace_fcall_later:;
if (current_scope[str]->children[0]->isConst())
newNode = current_scope[str]->children[0]->clone();
}
- else if (at_zero && current_scope.count(str) > 0 && (current_scope[str]->type == AST_WIRE || current_scope[str]->type == AST_AUTOWIRE)) {
+ else if (at_zero && current_scope.count(str) > 0) {
+ AstNode *node = current_scope[str];
+ if (node->type == AST_WIRE || node->type == AST_AUTOWIRE || node->type == AST_MEMORY)
+ newNode = mkconst_int(0, sign_hint, width_hint);
+ }
+ break;
+ case AST_MEMRD:
+ if (at_zero) {
newNode = mkconst_int(0, sign_hint, width_hint);
}
break;
@@ -3683,12 +3716,12 @@ apply_newNode:
return did_something;
}
-static void replace_result_wire_name_in_function(AstNode *node, std::string &from, std::string &to)
+void AstNode::replace_result_wire_name_in_function(const std::string &from, const std::string &to)
{
- for (auto &it : node->children)
- replace_result_wire_name_in_function(it, from, to);
- if (node->str == from)
- node->str = to;
+ for (AstNode *child : children)
+ child->replace_result_wire_name_in_function(from, to);
+ if (str == from && type != AST_FCALL && type != AST_TCALL)
+ str = to;
}
// replace a readmem[bh] TCALL ast node with a block of memory assignments
@@ -3881,7 +3914,7 @@ void AstNode::expand_genblock(std::string index_var, std::string prefix, std::ma
name_map[child->str] = new_name;
if (child->type == AST_FUNCTION)
- replace_result_wire_name_in_function(child, child->str, new_name);
+ child->replace_result_wire_name_in_function(child->str, new_name);
else
child->str = new_name;
current_scope[new_name] = child;
@@ -4461,15 +4494,31 @@ bool AstNode::detect_latch(const std::string &var)
bool AstNode::has_const_only_constructs(bool &recommend_const_eval)
{
+ std::set<std::string> visited;
+ return has_const_only_constructs(visited, recommend_const_eval);
+}
+
+bool AstNode::has_const_only_constructs(std::set<std::string>& visited, bool &recommend_const_eval)
+{
+ if (type == AST_FUNCTION || type == AST_TASK)
+ {
+ if (visited.count(str))
+ {
+ recommend_const_eval = true;
+ return false;
+ }
+ visited.insert(str);
+ }
+
if (type == AST_FOR)
recommend_const_eval = true;
if (type == AST_WHILE || type == AST_REPEAT)
return true;
if (type == AST_FCALL && current_scope.count(str))
- if (current_scope[str]->has_const_only_constructs(recommend_const_eval))
+ if (current_scope[str]->has_const_only_constructs(visited, recommend_const_eval))
return true;
for (auto child : children)
- if (child->AstNode::has_const_only_constructs(recommend_const_eval))
+ if (child->AstNode::has_const_only_constructs(visited, recommend_const_eval))
return true;
return false;
}
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 31c77d39c..cf3bf1070 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -55,7 +55,7 @@ USING_YOSYS_NAMESPACE
# error "Only Symbiotic EDA flavored Verific is supported. Please contact office@symbioticeda.com for commercial support for Yosys+Verific."
#endif
-#if SYMBIOTIC_VERIFIC_API_VERSION < 20201001
+#if SYMBIOTIC_VERIFIC_API_VERSION < 20201101
# error "Please update your version of Symbiotic EDA flavored Verific."
#endif
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index ea23139e2..752f7a7a8 100644
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -321,7 +321,6 @@ struct define_body_t
define_map_t::define_map_t()
{
add("YOSYS", "1");
- add(formal_mode ? "FORMAL" : "SYNTHESIS", "1");
}
// We must define this destructor here (rather than relying on the default), because we need to
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 2e9c9b2e2..5319a45ad 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -446,6 +446,9 @@ struct VerilogFrontend : public Frontend {
}
break;
}
+
+ defines_map.add(formal_mode ? "FORMAL" : "SYNTHESIS", "1");
+
extra_args(f, filename, args, argidx);
log_header(design, "Executing Verilog-2005 frontend: %s\n", filename.c_str());
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 678ce6c87..6c4b06d7f 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -884,7 +884,11 @@ task_func_args:
task_func_port:
attr wire_type range {
+ bool prev_was_input = true;
+ bool prev_was_output = false;
if (albuf) {
+ prev_was_input = astbuf1->is_input;
+ prev_was_output = astbuf1->is_output;
delete astbuf1;
if (astbuf2 != NULL)
delete astbuf2;
@@ -893,6 +897,12 @@ task_func_port:
albuf = $1;
astbuf1 = $2;
astbuf2 = checkRange(astbuf1, $3);
+ if (!astbuf1->is_input && !astbuf1->is_output) {
+ if (!sv_mode)
+ frontend_verilog_yyerror("task/function argument direction missing");
+ astbuf1->is_input = prev_was_input;
+ astbuf1->is_output = prev_was_output;
+ }
} wire_name |
{
if (!astbuf1) {
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-11 03:01:33 +0000