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-rw-r--r--frontends/verific/verific.cc2
1 files changed, 2 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 8b42ca8c1..84e5e6736 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -429,6 +429,8 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
import_attributes(wire->attributes, port);
module->add(wire);
+ wire->port_id = nl->IndexOf(port) + 1;
+
if (port->GetDir() == DIR_INOUT || port->GetDir() == DIR_IN)
wire->port_input = true;
if (port->GetDir() == DIR_INOUT || port->GetDir() == DIR_OUT)