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-rw-r--r--frontends/verific/example.sv18
1 files changed, 18 insertions, 0 deletions
diff --git a/frontends/verific/example.sv b/frontends/verific/example.sv
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+++ b/frontends/verific/example.sv
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+module top (
+ input clk, rst,
+ output reg [3:0] cnt
+);
+ initial cnt = 0;
+
+ always @(posedge clk) begin
+ if (rst)
+ cnt <= 0;
+ else
+ cnt <= cnt + 4'd 1;
+ end
+
+ always @(posedge clk) begin
+ assume (cnt != 10);
+ assert (cnt != 15);
+ end
+endmodule