4 files changed, 70 insertions, 8 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 82b4edef1..29795590c 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -44,7 +44,8 @@ namespace AST {
 
 // instanciate global variables (private API)
 namespace AST_INTERNAL {
-	bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
+	bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
+	bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
 	AstNode *current_ast, *current_ast_mod;
 	std::map<std::string, AstNode*> current_scope;
 	const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr = NULL;
@@ -175,7 +176,7 @@ bool AstNode::get_bool_attribute(RTLIL::IdString id)
 
 // create new node (AstNode constructor)
 // (the optional child arguments make it easier to create AST trees)
-AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2)
+AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *child3)
 {
 	static unsigned int hashidx_count = 123456789;
 	hashidx_count = mkhash_xorshift(hashidx_count);
@@ -203,6 +204,8 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2)
 		children.push_back(child1);
 	if (child2)
 		children.push_back(child2);
+	if (child3)
+		children.push_back(child3);
 }
 
 // create a (deep recursive) copy of a node
@@ -969,16 +972,25 @@ static AstModule* process_module(AstNode *ast, bool defer)
 	current_module->icells = flag_icells;
 	current_module->autowire = flag_autowire;
 	current_module->fixup_ports();
+
+	if (flag_dump_rtlil) {
+		log("Dumping generated RTLIL:\n");
+		log_module(current_module);
+		log("--- END OF RTLIL DUMP ---\n");
+	}
+
 	return current_module;
 }
 
 // create AstModule instances for all modules in the AST tree and add them to 'design'
-void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire)
+void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil,
+		bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire)
 {
 	current_ast = ast;
 	flag_dump_ast1 = dump_ast1;
 	flag_dump_ast2 = dump_ast2;
 	flag_dump_vlog = dump_vlog;
+	flag_dump_rtlil = dump_rtlil;
 	flag_nolatches = nolatches;
 	flag_nomeminit = nomeminit;
 	flag_nomem2reg = nomem2reg;
@@ -1023,9 +1035,8 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 
 			design->add(process_module(*it, defer));
 		}
-		else if ((*it)->type == AST_PACKAGE){
+		else if ((*it)->type == AST_PACKAGE)
 			design->verilog_packages.push_back((*it)->clone());
-		}
 		else
 			global_decls.push_back(*it);
 	}
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 5310bcadb..530c11ba5 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -187,7 +187,7 @@ namespace AST
 		int linenum;
 
 		// creating and deleting nodes
-		AstNode(AstNodeType type = AST_NONE, AstNode *child1 = NULL, AstNode *child2 = NULL);
+		AstNode(AstNodeType type = AST_NONE, AstNode *child1 = NULL, AstNode *child2 = NULL, AstNode *child3 = NULL);
 		AstNode *clone();
 		void cloneInto(AstNode *other);
 		void delete_children();
@@ -272,7 +272,8 @@ namespace AST
 	};
 
 	// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
-	void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire);
+	void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit,
+			bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire);
 
 	// parametric modules are supported directly by the AST library
 	// therefore we need our own derivate of RTLIL::Module with overloaded virtual functions
@@ -302,7 +303,8 @@ namespace AST
 namespace AST_INTERNAL
 {
 	// internal state variables
-	extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
+	extern bool flag_dump_ast1, flag_dump_ast2, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
+	extern bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
 	extern AST::AstNode *current_ast, *current_ast_mod;
 	extern std::map<std::string, AST::AstNode*> current_scope;
 	extern const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr;
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 2fb95ff5a..04cdb9416 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -750,6 +750,19 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 		width_hint = max(width_hint, this_width);
 		break;
 
+	case AST_FCALL:
+		if (str == "\\$anyconst" || str == "\\$aconst") {
+			if (GetSize(children) == 1) {
+				while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
+				if (children[0]->type != AST_CONSTANT)
+					log_error("System function %s called with non-const argument at %s:%d!\n",
+							RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum);
+				width_hint = max(width_hint, int(children[0]->asInt(true)));
+			}
+			break;
+		}
+		/* fall through */
+
 	// everything should have been handled above -> print error if not.
 	default:
 		for (auto f : log_files)
@@ -1427,6 +1440,38 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			delete always;
 		} break;
 
+	case AST_FCALL: {
+			if (str == "\\$anyconst" || str == "\\$aconst")
+			{
+				string myid = stringf("%s$%d", RTLIL::unescape_id(str).c_str(), autoidx++);
+				int width = width_hint;
+
+				if (GetSize(children) > 1)
+					log_error("System function %s got %d arguments, expected 1 or 0 at %s:%d.\n",
+							RTLIL::unescape_id(str).c_str(), GetSize(children), filename.c_str(), linenum);
+
+				if (GetSize(children) == 1) {
+					if (children[0]->type != AST_CONSTANT)
+						log_error("System function %s called with non-const argument at %s:%d!\n",
+								RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum);
+					width = children[0]->asInt(true);
+				}
+
+				if (width <= 0)
+					log_error("Failed to detect width of %s at %s:%d!\n",
+							RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum);
+
+				Cell *cell = current_module->addCell(myid, str.substr(1));
+				cell->parameters["\\WIDTH"] = width;
+
+				Wire *wire = current_module->addWire(myid + "_wire", width);
+				cell->setPort("\\Y", wire);
+
+				is_signed = sign_hint;
+				return SigSpec(wire);
+			}
+		} /* fall through */
+
 	// everything should have been handled above -> print error if not.
 	default:
 		for (auto f : log_files)
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 9f88cddc2..79dc3b7c8 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1655,6 +1655,10 @@ skip_dynamic_range_lvalue_expansion:;
 				goto apply_newNode;
 			}
 
+			// $anyconst and $aconst are mapped in AstNode::genRTLIL()
+			if (str == "\\$anyconst" || str == "\\$aconst")
+				return false;
+
 			if (str == "\\$clog2")
 			{
 				if (children.size() != 1)