diff options
Diffstat (limited to 'frontends/aiger/aigerparse.cc')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 5c862b8f0..426e88e53 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -162,9 +162,15 @@ void AigerReader::parse_aiger() int width = wp.second + 1; RTLIL::Wire *wire = module->wire(name); - if (wire) + if (wire) { + RTLIL::Cell* driver = module->cell(stringf("%slut", wire->name.c_str())); + module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0))); + if (driver) + module->rename(driver, stringf("%slut", wire->name.c_str())); + } + // Do not make ports with a mix of input/output into // wide ports bool port_input = false, port_output = false; @@ -408,9 +414,15 @@ void AigerReader::parse_xaiger() int width = wp.second + 1; RTLIL::Wire *wire = module->wire(name); - if (wire) + if (wire) { + RTLIL::Cell* driver = module->cell(stringf("%slut", wire->name.c_str())); + module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0))); + if (driver) + module->rename(driver, stringf("%slut", wire->name.c_str())); + } + // Do not make ports with a mix of input/output into // wide ports bool port_input = false, port_output = false; |