diff options
Diffstat (limited to 'examples/smtbmc')
| -rw-r--r-- | examples/smtbmc/.gitignore | 2 | ||||
| -rw-r--r-- | examples/smtbmc/Makefile | 11 | ||||
| -rw-r--r-- | examples/smtbmc/demo6.v | 14 |
3 files changed, 25 insertions, 2 deletions
diff --git a/examples/smtbmc/.gitignore b/examples/smtbmc/.gitignore index 88d264c63..ba7a1c9c6 100644 --- a/examples/smtbmc/.gitignore +++ b/examples/smtbmc/.gitignore @@ -16,3 +16,5 @@ demo4.yslog demo5.smt2 demo5.vcd demo5.yslog +demo6.smt2 +demo6.yslog diff --git a/examples/smtbmc/Makefile b/examples/smtbmc/Makefile index a2d4f444b..4fb0848f5 100644 --- a/examples/smtbmc/Makefile +++ b/examples/smtbmc/Makefile @@ -1,5 +1,5 @@ -all: demo1 demo2 demo3 demo4 +all: demo1 demo2 demo3 demo4 demo5 demo6 demo1: demo1.smt2 yosys-smtbmc --dump-vcd demo1.vcd demo1.smt2 @@ -19,6 +19,9 @@ demo4: demo4.smt2 demo5: demo5.smt2 yosys-smtbmc -g -t 50 --dump-vcd demo5.vcd demo5.smt2 +demo6: demo6.smt2 + yosys-smtbmc -t 1 demo6.smt2 + demo1.smt2: demo1.v yosys -ql demo1.yslog -p 'read_verilog -formal demo1.v; prep -top demo1 -nordff; write_smt2 -wires demo1.smt2' @@ -34,12 +37,16 @@ demo4.smt2: demo4.v demo5.smt2: demo5.v yosys -ql demo5.yslog -p 'read_verilog -formal demo5.v; prep -top demo5 -nordff; write_smt2 -wires demo5.smt2' +demo6.smt2: demo6.v + yosys -ql demo6.yslog -p 'read_verilog demo6.v; prep -top demo6 -nordff; assertpmux; opt -keepdc -fast; write_smt2 -wires demo6.smt2' + clean: rm -f demo1.yslog demo1.smt2 demo1.vcd rm -f demo2.yslog demo2.smt2 demo2.vcd demo2.smtc demo2_tb.v demo2_tb demo2_tb.vcd rm -f demo3.yslog demo3.smt2 demo3.vcd rm -f demo4.yslog demo4.smt2 demo4.vcd rm -f demo5.yslog demo5.smt2 demo5.vcd + rm -f demo6.yslog demo6.smt2 -.PHONY: demo1 demo2 demo3 demo4 demo5 clean +.PHONY: demo1 demo2 demo3 demo4 demo5 demo6 clean diff --git a/examples/smtbmc/demo6.v b/examples/smtbmc/demo6.v new file mode 100644 index 000000000..62a72e2a8 --- /dev/null +++ b/examples/smtbmc/demo6.v @@ -0,0 +1,14 @@ +// Demo for assertpmux + +module demo6 (input A, B, C, D, E, output reg Y); + always @* begin + Y = 0; + if (A != B) begin + (* parallel_case *) + case (C) + A: Y = D; + B: Y = E; + endcase + end + end +endmodule |