diff options
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index d8160c97b..d7fe4c4e2 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -571,6 +571,28 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) return true; } + if (cell->type == "$slice") + { + fprintf(f, "%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->connections["\\Y"]); + fprintf(f, " = "); + dump_sigspec(f, cell->connections["\\A"]); + fprintf(f, " >> %d;\n", cell->parameters.at("\\OFFSET").as_int()); + return true; + } + + if (cell->type == "$concat") + { + fprintf(f, "%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->connections["\\Y"]); + fprintf(f, " = { "); + dump_sigspec(f, cell->connections["\\B"]); + fprintf(f, " , "); + dump_sigspec(f, cell->connections["\\A"]); + fprintf(f, " };\n"); + return true; + } + if (cell->type == "$dff" || cell->type == "$adff") { RTLIL::SigSpec sig_clk, sig_arst, val_arst; |