diff options
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/spice/spice.cc | 2 | ||||
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index 4bc8710e9..653a9f22d 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -80,7 +80,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de for (RTLIL::Wire *wire : ports) { log_assert(wire != NULL); RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width); - if (cell->connections().count(wire->name) > 0) { + if (cell->has(wire->name)) { sig = sigmap(cell->connections().at(wire->name)); sig.extend(wire->width, false); } diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 6bef90e38..d9186c043 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -301,7 +301,7 @@ void dump_cell_expr_port(FILE *f, RTLIL::Cell *cell, std::string port, bool gen_ std::string cellname(RTLIL::Cell *cell) { - if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->connections().count("\\Q") > 0) + if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->has("\\Q")) { RTLIL::SigSpec sig = cell->get("\\Q"); if (SIZE(sig) != 1 || sig.is_fully_const()) @@ -908,7 +908,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) for (auto &it : module->cells) { RTLIL::Cell *cell = it.second; - if (!reg_ct.cell_known(cell->type) || cell->connections().count("\\Q") == 0) + if (!reg_ct.cell_known(cell->type) || !cell->has("\\Q")) continue; RTLIL::SigSpec sig = cell->get("\\Q"); |