2 files changed, 50 insertions, 0 deletions
diff --git a/backends/btor/btor.ys b/backends/btor/btor.ys
new file mode 100644
index 000000000..7f3882b57
--- /dev/null
+++ b/backends/btor/btor.ys
@@ -0,0 +1,15 @@
+proc; 
+opt; opt_const -mux_undef; opt;
+rename -hide;;;
+#converting pmux to mux
+techmap -map techlibs/common/pmux2mux.v;;
+memory -nomap;;
+#flatten design
+flatten;;
+#converting asyn memory write to syn memory
+memory_unpack; 
+#cell output to be a single wire
+splitnets -driver;
+setundef -zero -undriven;
+opt;;;
+
diff --git a/backends/btor/verilog2btor.sh b/backends/btor/verilog2btor.sh
new file mode 100755
index 000000000..ef0134e07
--- /dev/null
+++ b/backends/btor/verilog2btor.sh
@@ -0,0 +1,35 @@
+#!/bin/sh
+
+#
+# Script to writing btor from verilog design
+#
+
+if [ "$#" -ne 3 ]; then
+  echo "Usage: $0 input.v output.btor top-module-name" >&2
+  exit 1
+fi
+if ! [ -e "$1" ]; then
+  echo "$1 not found" >&2
+  exit 1
+fi
+
+FULL_PATH=$(readlink -f $1)
+DIR=$(dirname $FULL_PATH)
+
+./yosys -q -p "
+read_verilog $1; 
+hierarchy -top $3; 
+hierarchy -libdir $DIR; 
+hierarchy -check; 
+proc; 
+opt; opt_const -mux_undef; opt;
+rename -hide;;;
+techmap -map $YOSYS_HOME/techlibs/common/pmux2mux.v;;
+memory -nomap;;
+flatten;;
+memory_unpack; 
+splitnets -driver;
+setundef -zero -undriven;
+opt;;;
+write_btor $2;"
+