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-rw-r--r--backends/edif/edif.cc216
1 files changed, 108 insertions, 108 deletions
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index 1748ed810..ccedd91d2 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -26,9 +26,9 @@
#include "kernel/celltypes.h"
#include "kernel/log.h"
#include <string>
-#include <assert.h>
-#define EDIF_NAME(_id) edif_names(RTLIL::unescape_id(_id)).c_str()
+#define EDIF_DEF(_id) edif_names(RTLIL::unescape_id(_id), true).c_str()
+#define EDIF_REF(_id) edif_names(RTLIL::unescape_id(_id), false).c_str()
namespace
{
@@ -40,8 +40,13 @@ namespace
EdifNames() : counter(1) { }
- std::string operator()(std::string id)
+ std::string operator()(std::string id, bool define)
{
+ if (define) {
+ std::string new_id = operator()(id, false);
+ return new_id != id ? stringf("(rename %s \"%s\")", new_id.c_str(), id.c_str()) : id;
+ }
+
if (name_map.count(id) > 0)
return name_map.at(id);
if (generated_names.count(id) > 0)
@@ -74,7 +79,7 @@ namespace
}
generated_names.insert(gen_name);
name_map[id] = gen_name;
- return stringf("(rename %s \"%s\")", gen_name.c_str(), id.c_str());
+ return gen_name;
}
};
}
@@ -98,12 +103,12 @@ struct EdifBackend : public Backend {
log("is targeted.\n");
log("\n");
}
- virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+ virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing EDIF backend.\n");
std::string top_module_name;
- std::map<std::string, std::set<std::string>> lib_cell_ports;
+ std::map<RTLIL::IdString, std::set<RTLIL::IdString>> lib_cell_ports;
CellTypes ct(design);
EdifNames edif_names;
@@ -119,31 +124,31 @@ struct EdifBackend : public Backend {
extra_args(f, filename, args, argidx);
if (top_module_name.empty())
- for (auto & mod_it:design->modules)
+ for (auto & mod_it:design->modules_)
if (mod_it.second->get_bool_attribute("\\top"))
- top_module_name = mod_it.first;
+ top_module_name = mod_it.first.str();
- for (auto module_it : design->modules)
+ for (auto module_it : design->modules_)
{
RTLIL::Module *module = module_it.second;
if (module->get_bool_attribute("\\blackbox"))
continue;
if (top_module_name.empty())
- top_module_name = module->name;
+ top_module_name = module->name.str();
if (module->processes.size() != 0)
log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
if (module->memories.size() != 0)
log_error("Found munmapped emories in module %s: unmapped memories are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
- for (auto cell_it : module->cells)
+ for (auto cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;
- if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) {
+ if (!design->modules_.count(cell->type) || design->modules_.at(cell->type)->get_bool_attribute("\\blackbox")) {
lib_cell_ports[cell->type];
- for (auto p : cell->connections) {
- if (p.second.width > 1)
+ for (auto p : cell->connections()) {
+ if (p.second.size() > 1)
log_error("Found multi-bit port %s on library cell %s.%s (%s): not supported in EDIF backend!\n",
RTLIL::id2cstr(p.first), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
lib_cell_ports[cell->type].insert(p.first);
@@ -155,38 +160,38 @@ struct EdifBackend : public Backend {
if (top_module_name.empty())
log_error("No module found in design!\n");
- fprintf(f, "(edif %s\n", EDIF_NAME(top_module_name));
- fprintf(f, " (edifVersion 2 0 0)\n");
- fprintf(f, " (edifLevel 0)\n");
- fprintf(f, " (keywordMap (keywordLevel 0))\n");
- fprintf(f, " (comment \"Generated by %s\")\n", yosys_version_str);
-
- fprintf(f, " (external LIB\n");
- fprintf(f, " (edifLevel 0)\n");
- fprintf(f, " (technology (numberDefinition))\n");
-
- fprintf(f, " (cell GND\n");
- fprintf(f, " (cellType GENERIC)\n");
- fprintf(f, " (view VIEW_NETLIST\n");
- fprintf(f, " (viewType NETLIST)\n");
- fprintf(f, " (interface (port G (direction OUTPUT)))\n");
- fprintf(f, " )\n");
- fprintf(f, " )\n");
-
- fprintf(f, " (cell VCC\n");
- fprintf(f, " (cellType GENERIC)\n");
- fprintf(f, " (view VIEW_NETLIST\n");
- fprintf(f, " (viewType NETLIST)\n");
- fprintf(f, " (interface (port P (direction OUTPUT)))\n");
- fprintf(f, " )\n");
- fprintf(f, " )\n");
+ *f << stringf("(edif %s\n", EDIF_DEF(top_module_name));
+ *f << stringf(" (edifVersion 2 0 0)\n");
+ *f << stringf(" (edifLevel 0)\n");
+ *f << stringf(" (keywordMap (keywordLevel 0))\n");
+ *f << stringf(" (comment \"Generated by %s\")\n", yosys_version_str);
+
+ *f << stringf(" (external LIB\n");
+ *f << stringf(" (edifLevel 0)\n");
+ *f << stringf(" (technology (numberDefinition))\n");
+
+ *f << stringf(" (cell GND\n");
+ *f << stringf(" (cellType GENERIC)\n");
+ *f << stringf(" (view VIEW_NETLIST\n");
+ *f << stringf(" (viewType NETLIST)\n");
+ *f << stringf(" (interface (port G (direction OUTPUT)))\n");
+ *f << stringf(" )\n");
+ *f << stringf(" )\n");
+
+ *f << stringf(" (cell VCC\n");
+ *f << stringf(" (cellType GENERIC)\n");
+ *f << stringf(" (view VIEW_NETLIST\n");
+ *f << stringf(" (viewType NETLIST)\n");
+ *f << stringf(" (interface (port P (direction OUTPUT)))\n");
+ *f << stringf(" )\n");
+ *f << stringf(" )\n");
for (auto &cell_it : lib_cell_ports) {
- fprintf(f, " (cell %s\n", EDIF_NAME(cell_it.first));
- fprintf(f, " (cellType GENERIC)\n");
- fprintf(f, " (view VIEW_NETLIST\n");
- fprintf(f, " (viewType NETLIST)\n");
- fprintf(f, " (interface\n");
+ *f << stringf(" (cell %s\n", EDIF_DEF(cell_it.first));
+ *f << stringf(" (cellType GENERIC)\n");
+ *f << stringf(" (view VIEW_NETLIST\n");
+ *f << stringf(" (viewType NETLIST)\n");
+ *f << stringf(" (interface\n");
for (auto &port_it : cell_it.second) {
const char *dir = "INOUT";
if (ct.cell_known(cell_it.first)) {
@@ -195,23 +200,23 @@ struct EdifBackend : public Backend {
else if (!ct.cell_input(cell_it.first, port_it))
dir = "OUTPUT";
}
- fprintf(f, " (port %s (direction %s))\n", EDIF_NAME(port_it), dir);
+ *f << stringf(" (port %s (direction %s))\n", EDIF_DEF(port_it), dir);
}
- fprintf(f, " )\n");
- fprintf(f, " )\n");
- fprintf(f, " )\n");
+ *f << stringf(" )\n");
+ *f << stringf(" )\n");
+ *f << stringf(" )\n");
}
- fprintf(f, " )\n");
+ *f << stringf(" )\n");
std::vector<RTLIL::Module*> sorted_modules;
// extract module dependencies
std::map<RTLIL::Module*, std::set<RTLIL::Module*>> module_deps;
- for (auto &mod_it : design->modules) {
+ for (auto &mod_it : design->modules_) {
module_deps[mod_it.second] = std::set<RTLIL::Module*>();
- for (auto &cell_it : mod_it.second->cells)
- if (design->modules.count(cell_it.second->type) > 0)
- module_deps[mod_it.second].insert(design->modules.at(cell_it.second->type));
+ for (auto &cell_it : mod_it.second->cells_)
+ if (design->modules_.count(cell_it.second->type) > 0)
+ module_deps[mod_it.second].insert(design->modules_.at(cell_it.second->type));
}
// simple good-enough topological sort
@@ -233,9 +238,9 @@ struct EdifBackend : public Backend {
}
- fprintf(f, " (library DESIGN\n");
- fprintf(f, " (edifLevel 0)\n");
- fprintf(f, " (technology (numberDefinition))\n");
+ *f << stringf(" (library DESIGN\n");
+ *f << stringf(" (edifLevel 0)\n");
+ *f << stringf(" (technology (numberDefinition))\n");
for (auto module : sorted_modules)
{
if (module->get_bool_attribute("\\blackbox"))
@@ -244,12 +249,12 @@ struct EdifBackend : public Backend {
SigMap sigmap(module);
std::map<RTLIL::SigSpec, std::set<std::string>> net_join_db;
- fprintf(f, " (cell %s\n", EDIF_NAME(module->name));
- fprintf(f, " (cellType GENERIC)\n");
- fprintf(f, " (view VIEW_NETLIST\n");
- fprintf(f, " (viewType NETLIST)\n");
- fprintf(f, " (interface\n");
- for (auto &wire_it : module->wires) {
+ *f << stringf(" (cell %s\n", EDIF_DEF(module->name));
+ *f << stringf(" (cellType GENERIC)\n");
+ *f << stringf(" (view VIEW_NETLIST\n");
+ *f << stringf(" (viewType NETLIST)\n");
+ *f << stringf(" (interface\n");
+ for (auto &wire_it : module->wires_) {
RTLIL::Wire *wire = wire_it.second;
if (wire->port_id == 0)
continue;
@@ -259,31 +264,31 @@ struct EdifBackend : public Backend {
else if (!wire->port_input)
dir = "OUTPUT";
if (wire->width == 1) {
- fprintf(f, " (port %s (direction %s))\n", EDIF_NAME(wire->name), dir);
+ *f << stringf(" (port %s (direction %s))\n", EDIF_DEF(wire->name), dir);
RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire));
- net_join_db[sig].insert(stringf("(portRef %s)", EDIF_NAME(wire->name)));
+ net_join_db[sig].insert(stringf("(portRef %s)", EDIF_REF(wire->name)));
} else {
- fprintf(f, " (port (array %s %d) (direction %s))\n", EDIF_NAME(wire->name), wire->width, dir);
+ *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEF(wire->name), wire->width, dir);
for (int i = 0; i < wire->width; i++) {
- RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, 1, i));
- net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_NAME(wire->name), i));
+ RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i));
+ net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i));
}
}
}
- fprintf(f, " )\n");
- fprintf(f, " (contents\n");
- fprintf(f, " (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n");
- fprintf(f, " (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n");
- for (auto &cell_it : module->cells) {
+ *f << stringf(" )\n");
+ *f << stringf(" (contents\n");
+ *f << stringf(" (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n");
+ *f << stringf(" (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n");
+ for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
- fprintf(f, " (instance %s\n", EDIF_NAME(cell->name));
- fprintf(f, " (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_NAME(cell->type),
+ *f << stringf(" (instance %s\n", EDIF_DEF(cell->name));
+ *f << stringf(" (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type),
lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : "");
for (auto &p : cell->parameters)
if ((p.second.flags & RTLIL::CONST_FLAG_STRING) != 0)
- fprintf(f, "\n (property %s (string \"%s\"))", EDIF_NAME(p.first), p.second.decode_string().c_str());
+ *f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(p.first), p.second.decode_string().c_str());
else if (p.second.bits.size() <= 32 && RTLIL::SigSpec(p.second).is_fully_def())
- fprintf(f, "\n (property %s (integer %u))", EDIF_NAME(p.first), p.second.as_int());
+ *f << stringf("\n (property %s (integer %u))", EDIF_DEF(p.first), p.second.as_int());
else {
std::string hex_string = "";
for (size_t i = 0; i < p.second.bits.size(); i += 4) {
@@ -295,53 +300,48 @@ struct EdifBackend : public Backend {
char digit_str[2] = { "0123456789abcdef"[digit_value], 0 };
hex_string = std::string(digit_str) + hex_string;
}
- fprintf(f, "\n (property %s (string \"%s\"))", EDIF_NAME(p.first), hex_string.c_str());
+ *f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(p.first), hex_string.c_str());
}
- fprintf(f, ")\n");
- for (auto &p : cell->connections) {
+ *f << stringf(")\n");
+ for (auto &p : cell->connections()) {
RTLIL::SigSpec sig = sigmap(p.second);
- sig.expand();
- for (int i = 0; i < sig.width; i++) {
- RTLIL::SigSpec sigbit(sig.chunks.at(i));
- std::string portname = sig.width > 1 ? stringf("%s[%d]", RTLIL::id2cstr(p.first), i) : RTLIL::id2cstr(p.first);
- net_join_db[sigbit].insert(stringf("(portRef %s (instanceRef %s))", edif_names(portname).c_str(), EDIF_NAME(cell->name)));
- }
+ for (int i = 0; i < SIZE(sig); i++)
+ if (sig.size() == 1)
+ net_join_db[sig[i]].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name)));
+ else
+ net_join_db[sig[i]].insert(stringf("(portRef (member %s %d) (instanceRef %s))", EDIF_REF(p.first), i, EDIF_REF(cell->name)));
}
}
for (auto &it : net_join_db) {
- RTLIL::SigSpec sig = it.first;
- sig.optimize();
- log_assert(sig.width == 1);
- if (sig.chunks.at(0).wire == NULL) {
- if (sig.chunks.at(0).data.bits.at(0) != RTLIL::State::S0 && sig.chunks.at(0).data.bits.at(0) != RTLIL::State::S1)
- continue;
- }
+ RTLIL::SigBit sig = it.first;
+ if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1)
+ continue;
std::string netname = log_signal(sig);
for (size_t i = 0; i < netname.size(); i++)
if (netname[i] == ' ' || netname[i] == '\\')
netname.erase(netname.begin() + i--);
- fprintf(f, " (net %s (joined\n", edif_names(netname).c_str());
+ *f << stringf(" (net %s (joined\n", EDIF_DEF(netname));
for (auto &ref : it.second)
- fprintf(f, " %s\n", ref.c_str());
- if (sig.chunks.at(0).wire == NULL) {
- if (sig.chunks.at(0).data.bits.at(0) == RTLIL::State::S0)
- fprintf(f, " (portRef G (instanceRef GND))\n");
- if (sig.chunks.at(0).data.bits.at(0) == RTLIL::State::S1)
- fprintf(f, " (portRef P (instanceRef VCC))\n");
+ *f << stringf(" %s\n", ref.c_str());
+ if (sig.wire == NULL) {
+ if (sig == RTLIL::State::S0)
+ *f << stringf(" (portRef G (instanceRef GND))\n");
+ if (sig == RTLIL::State::S1)
+ *f << stringf(" (portRef P (instanceRef VCC))\n");
}
- fprintf(f, " ))\n");
+ *f << stringf(" ))\n");
}
- fprintf(f, " )\n");
- fprintf(f, " )\n");
- fprintf(f, " )\n");
+ *f << stringf(" )\n");
+ *f << stringf(" )\n");
+ *f << stringf(" )\n");
}
- fprintf(f, " )\n");
+ *f << stringf(" )\n");
- fprintf(f, " (design %s\n", EDIF_NAME(top_module_name));
- fprintf(f, " (cellRef %s (libraryRef DESIGN))\n", EDIF_NAME(top_module_name));
- fprintf(f, " )\n");
+ *f << stringf(" (design %s\n", EDIF_DEF(top_module_name));
+ *f << stringf(" (cellRef %s (libraryRef DESIGN))\n", EDIF_REF(top_module_name));
+ *f << stringf(" )\n");
- fprintf(f, ")\n");
+ *f << stringf(")\n");
}
} EdifBackend;
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-22 15:32:37 +0000