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Diffstat (limited to 'README')
| -rw-r--r-- | README | 7 |
1 files changed, 7 insertions, 0 deletions
@@ -384,9 +384,16 @@ from SystemVerilog: form. In module context: "assert property (<expression>);" and within an always block: "assert(<expression>);". It is transformed to a $assert cell. +- The "assume" and "expect" statements from SystemVerilog are also + supported. The same limitations as with the "assert" statement apply. + - The keywords "always_comb", "always_ff" and "always_latch", "logic" and "bit" are supported. +- SystemVerilog packages are supported. Once a SystemVerilog file is read + into a design with "read_verilog", all its packages are available to + SystemVerilog files being read into the same design afterwards. + Building the documentation ========================== |