1 files changed, 1 insertions, 0 deletions
diff --git a/CHANGELOG b/CHANGELOG
index f0a0d0fae..50c611b8d 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -38,6 +38,7 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Improvements in pmgen: slices, choices, define, generate
     - Added "xilinx_srl" for Xilinx shift register extraction
     - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
+    - Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
     - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
     - Added "xilinx_dsp" for Xilinx DSP packing
     - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)