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-rw-r--r--CHANGELOG3
1 files changed, 2 insertions, 1 deletions
diff --git a/CHANGELOG b/CHANGELOG
index 73115600c..c280f4f12 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -22,6 +22,7 @@ Yosys 0.8 .. Yosys 0.8-dev
- Added "muxcover -dmux=<cost>"
- Added "muxcover -nopartial"
- Added "muxpack" pass
+ - Added "pmux2shiftx -norange"
- Added "write_xaiger" backend
- Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
- Added "synth_xilinx -abc9" (experimental)
@@ -51,7 +52,7 @@ Yosys 0.7 .. Yosys 0.8
- Added Verilog $rtoi and $itor support
- Added "check -initdrv"
- Added "read_blif -wideports"
- - Added support for systemVerilog "++" and "--" operators
+ - Added support for SystemVerilog "++" and "--" operators
- Added support for SystemVerilog unique, unique0, and priority case
- Added "write_edif" options for edif "flavors"
- Added support for resetall compiler directive