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-rw-r--r--frontends/aiger/aigerparse.cc6
1 files changed, 6 insertions, 0 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index e8a355671..8d7588f88 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -722,8 +722,14 @@ void AigerReader::post_process()
module->fixup_ports();
design->add(module);
+ design->selection_stack.emplace_back(false);
+ RTLIL::Selection& sel = design->selection_stack.back();
+ sel.select(module);
+
Pass::call(design, "clean");
+ design->selection_stack.pop_back();
+
for (auto cell : module->cells().to_vector()) {
if (cell->type != "$lut") continue;
auto y_port = cell->getPort("\\Y").as_bit();