1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index b4657daca..6e8729256 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -269,7 +269,7 @@ endmodule
 module FDCE (
   (* abc_arrival=303 *)
   output reg Q,
-  (* clkbuf_sink *) 
+  (* clkbuf_sink *)
   input C,
   input CE, D, CLR
 );
@@ -289,7 +289,7 @@ endmodule
 module FDPE (
   (* abc_arrival=303 *)
   output reg Q,
-  (* clkbuf_sink *) 
+  (* clkbuf_sink *)
   input C,
   input CE, D, PRE
 );