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| -rw-r--r-- | tests/arch/xilinx/memory_params.ys | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tests/arch/xilinx/memory_params.ys b/tests/arch/xilinx/memory_params.ys index f279a4a6e..657629e0f 100644 --- a/tests/arch/xilinx/memory_params.ys +++ b/tests/arch/xilinx/memory_params.ys @@ -1,3 +1,5 @@ +## TODO: Not running equivalence checking because BRAM models does not exists +## currently. Checking instance counts instead. # Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 read_verilog ../common/memory_params.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp |