diff options
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 7bac1b974..d48c646c0 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -192,6 +192,7 @@ void pack_xilinx_simd(Module *module, const std::vector<Cell*> &selected_cells) SigSpec Y = lane->getPort("\\Y"); A.extend_u0(24, lane->getParam("\\A_SIGNED").as_bool()); B.extend_u0(24, lane->getParam("\\B_SIGNED").as_bool()); + C.append(A); AB.append(B); if (GetSize(Y) < 25) Y.append(module->addWire(NEW_ID, 25-GetSize(Y))); |