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-rw-r--r--passes/memory/memory.cc5
-rw-r--r--passes/memory/memory_dff.cc78
-rw-r--r--passes/memory/memory_nordff.cc2
-rw-r--r--techlibs/common/prep.cc13
-rw-r--r--tests/opt/opt_clean_mem.ys1
-rwxr-xr-xtests/tools/autotest.sh2
6 files changed, 19 insertions, 82 deletions
diff --git a/passes/memory/memory.cc b/passes/memory/memory.cc
index 282517992..9dec05db8 100644
--- a/passes/memory/memory.cc
+++ b/passes/memory/memory.cc
@@ -36,7 +36,7 @@ struct MemoryPass : public Pass {
log("This pass calls all the other memory_* passes in a useful order:\n");
log("\n");
log(" opt_mem\n");
- log(" memory_dff [-nordff] (-memx implies -nordff)\n");
+ log(" memory_dff (skipped if called with -nordff or -memx)\n");
log(" opt_clean\n");
log(" memory_share\n");
log(" opt_clean\n");
@@ -83,7 +83,8 @@ struct MemoryPass : public Pass {
extra_args(args, argidx, design);
Pass::call(design, "opt_mem");
- Pass::call(design, flag_nordff ? "memory_dff -nordff" : "memory_dff");
+ if (!flag_nordff)
+ Pass::call(design, "memory_dff");
Pass::call(design, "opt_clean");
Pass::call(design, "memory_share");
if (flag_memx)
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 64881672e..83c9d7631 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -33,7 +33,6 @@ struct MemoryDffWorker
vector<Cell*> dff_cells;
dict<SigBit, SigBit> invbits;
dict<SigBit, int> sigbit_users_count;
- pool<Cell*> forward_merged_dffs, candidate_dffs;
FfInitVals initvals;
MemoryDffWorker(Module *module) : module(module), sigmap(module)
@@ -113,7 +112,6 @@ struct MemoryDffWorker
bit = d;
clk = this_clk;
clk_polarity = this_clk_polarity;
- candidate_dffs.insert(cell);
goto replaced_this_bit;
}
@@ -135,8 +133,6 @@ struct MemoryDffWorker
for (auto cell : dff_cells)
{
- if (forward_merged_dffs.count(cell))
- continue;
if (!cell->type.in(ID($dff), ID($dffe)))
continue;
@@ -186,7 +182,6 @@ struct MemoryDffWorker
clk_polarity = this_clk_polarity;
en = this_en;
en_polarity = this_en_polarity;
- candidate_dffs.insert(cell);
goto replaced_this_bit;
}
@@ -197,51 +192,6 @@ struct MemoryDffWorker
return true;
}
- void handle_wr_cell(RTLIL::Cell *cell)
- {
- log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str());
-
- RTLIL::SigSpec clk = RTLIL::SigSpec(RTLIL::State::Sx);
- bool clk_polarity = 0;
- candidate_dffs.clear();
-
- RTLIL::SigSpec sig_addr = cell->getPort(ID::ADDR);
- if (!find_sig_before_dff(sig_addr, clk, clk_polarity)) {
- log("no (compatible) $dff for address input found.\n");
- return;
- }
-
- RTLIL::SigSpec sig_data = cell->getPort(ID::DATA);
- if (!find_sig_before_dff(sig_data, clk, clk_polarity)) {
- log("no (compatible) $dff for data input found.\n");
- return;
- }
-
- RTLIL::SigSpec sig_en = cell->getPort(ID::EN);
- if (!find_sig_before_dff(sig_en, clk, clk_polarity)) {
- log("no (compatible) $dff for enable input found.\n");
- return;
- }
-
- if (clk != RTLIL::SigSpec(RTLIL::State::Sx))
- {
- for (auto cell : candidate_dffs)
- forward_merged_dffs.insert(cell);
-
- cell->setPort(ID::CLK, clk);
- cell->setPort(ID::ADDR, sig_addr);
- cell->setPort(ID::DATA, sig_data);
- cell->setPort(ID::EN, sig_en);
- cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(1);
- cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity);
-
- log("merged $dff to cell.\n");
- return;
- }
-
- log("no (compatible) $dff found.\n");
- }
-
void disconnect_dff(RTLIL::SigSpec sig)
{
sigmap.apply(sig);
@@ -309,7 +259,7 @@ struct MemoryDffWorker
log("no (compatible) $dff found.\n");
}
- void run(bool flag_wr_only)
+ void run()
{
for (auto wire : module->wires()) {
if (wire->port_output)
@@ -337,51 +287,37 @@ struct MemoryDffWorker
}
for (auto cell : module->selected_cells())
- if (cell->type == ID($memwr) && !cell->parameters[ID::CLK_ENABLE].as_bool())
- handle_wr_cell(cell);
-
- if (!flag_wr_only)
- for (auto cell : module->selected_cells())
- if (cell->type == ID($memrd) && !cell->parameters[ID::CLK_ENABLE].as_bool())
- handle_rd_cell(cell);
+ if (cell->type == ID($memrd) && !cell->parameters[ID::CLK_ENABLE].as_bool())
+ handle_rd_cell(cell);
}
};
struct MemoryDffPass : public Pass {
- MemoryDffPass() : Pass("memory_dff", "merge input/output DFFs into memories") { }
+ MemoryDffPass() : Pass("memory_dff", "merge input/output DFFs into memory read ports") { }
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" memory_dff [options] [selection]\n");
log("\n");
- log("This pass detects DFFs at memory ports and merges them into the memory port.\n");
+ log("This pass detects DFFs at memory read ports and merges them into the memory port.\n");
log("I.e. it consumes an asynchronous memory port and the flip-flops at its\n");
log("interface and yields a synchronous memory port.\n");
log("\n");
- log(" -nordfff\n");
- log(" do not merge registers on read ports\n");
- log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
- bool flag_wr_only = false;
-
- log_header(design, "Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).\n");
+ log_header(design, "Executing MEMORY_DFF pass (merging $dff cells to $memrd).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
- if (args[argidx] == "-nordff" || args[argidx] == "-wr_only") {
- flag_wr_only = true;
- continue;
- }
break;
}
extra_args(args, argidx, design);
for (auto mod : design->selected_modules()) {
MemoryDffWorker worker(mod);
- worker.run(flag_wr_only);
+ worker.run();
}
}
} MemoryDffPass;
diff --git a/passes/memory/memory_nordff.cc b/passes/memory/memory_nordff.cc
index a4fdcfc38..bb853c483 100644
--- a/passes/memory/memory_nordff.cc
+++ b/passes/memory/memory_nordff.cc
@@ -33,7 +33,7 @@ struct MemoryNordffPass : public Pass {
log(" memory_nordff [options] [selection]\n");
log("\n");
log("This pass extracts FFs from memory read ports. This results in a netlist\n");
- log("similar to what one would get from calling memory_dff with -nordff.\n");
+ log("similar to what one would get from not calling memory_dff.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
diff --git a/techlibs/common/prep.cc b/techlibs/common/prep.cc
index 93b0910d6..132d6aec2 100644
--- a/techlibs/common/prep.cc
+++ b/techlibs/common/prep.cc
@@ -61,7 +61,7 @@ struct PrepPass : public ScriptPass
log(" do not run any of the memory_* passes\n");
log("\n");
log(" -rdff\n");
- log(" do not pass -nordff to 'memory_dff'. This enables merging of FFs into\n");
+ log(" call 'memory_dff'. This enables merging of FFs into\n");
log(" memory read ports.\n");
log("\n");
log(" -nokeepdc\n");
@@ -79,7 +79,7 @@ struct PrepPass : public ScriptPass
}
string top_module, fsm_opts;
- bool autotop, flatten, ifxmode, memxmode, nomemmode, nokeepdc, nordff;
+ bool autotop, flatten, ifxmode, memxmode, nomemmode, nokeepdc, rdff;
void clear_flags() override
{
@@ -91,7 +91,7 @@ struct PrepPass : public ScriptPass
memxmode = false;
nomemmode = false;
nokeepdc = false;
- nordff = true;
+ rdff = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -137,11 +137,11 @@ struct PrepPass : public ScriptPass
continue;
}
if (args[argidx] == "-nordff") {
- nordff = true;
+ rdff = false;
continue;
}
if (args[argidx] == "-rdff") {
- nordff = false;
+ rdff = true;
continue;
}
if (args[argidx] == "-nokeepdc") {
@@ -202,7 +202,8 @@ struct PrepPass : public ScriptPass
run(memxmode ? "wreduce -keepdc -memx" : "wreduce -keepdc");
}
if (!nomemmode) {
- run(string("memory_dff") + (help_mode ? " [-nordff]" : nordff ? " -nordff" : ""));
+ if (help_mode || rdff)
+ run("memory_dff", "(if -rdff)");
if (help_mode || memxmode)
run("memory_memx", "(if -memx)");
run("opt_clean");
diff --git a/tests/opt/opt_clean_mem.ys b/tests/opt/opt_clean_mem.ys
index b35b15871..d08943da4 100644
--- a/tests/opt/opt_clean_mem.ys
+++ b/tests/opt/opt_clean_mem.ys
@@ -22,7 +22,6 @@ endmodule
EOT
proc
-memory_dff
select -assert-count 2 t:$memrd
select -assert-count 1 t:$memwr
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 72a3d51eb..e4aef9917 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -197,7 +197,7 @@ do
test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.${refext}
if [ -n "$firrtl2verilog" ]; then
if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then
- "$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine; pmuxtree" ${bn}_ref.${refext}
+ "$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine; pmuxtree" ${bn}_ref.${refext}
$firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v
test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine" ${bn}_ref.fir.v
fi
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-22 07:33:36 +0000